公开(公告)号：US20100117138A1

公开(公告)日：2010-05-13

申请号：US12594673

申请日：2008-04-17

Applicant: Almudena Huerta ,  Michiel Jos Van Duuren ,  Nader Akil ,  Dusan Golubovic ,  Mohamed Boutchich

Inventor： Almudena Huerta ,  Michiel Jos Van Duuren ,  Nader Akil ,  Dusan Golubovic ,  Mohamed Boutchich

IPC: H01L29/792 ,  H01L21/336

CPC classification number: B82Y10/00 ,  G11C16/0433 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0203 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

Abstract: A memory cell (300, 500), the memory cell (300, 500) comprising a substrate (301), a nanowire (302) extending along a vertical trench formed in the substrate (301), a control gate (303) surrounding the nanowire (302), and a charge storage structure (320, 501) formed between the control gate (303) and the nanowire (302).

Abstract translation: 存储单元（300,500），包括基板（301）的存储单元（300,500），沿着形成在基板（301）中的垂直沟槽延伸的纳米线（302）;围绕该基板 纳米线（302）和形成在控制栅极（303）和纳米线（302）之间的电荷存储结构（320,501）。

公开(公告)号：US20090079494A1

公开(公告)日：2009-03-26

申请号：US12237822

申请日：2008-09-25

Applicant: Christoph Kerner ,  Wim Magnus ,  Dusan Golubovic

Inventor： Christoph Kerner ,  Wim Magnus ,  Dusan Golubovic

IPC: H01L39/22

CPC classification number: B82Y10/00 ,  G06N99/002 ,  G11C11/06 ,  G11C11/44 ,  Y10S505/832

Abstract: A method of operating a quantum system comprising computational elements, including an insulated ring of superconductive material, and semi-closed rings used as an interface between the computational elements and the external world, is disclosed. In one aspect, the method comprises providing an electrical signal, e.g. a current, in an input ring magnetically coupled to a computational element, which generates a magnetic field in the computational element and sensing the change in the current and/or voltage of an output element magnetically coupled to the computational element. The electrical input signal can be an AC signal or a DC signal. The computational element is electromagnetically coupled with other adjacent computational elements and/or with the interface elements. The corresponding magnetic flux between the computational elements and/or the interface elements acts as an information carrier. Ferromagnetic cores are used to improve the magnetic coupling between adjacent elements.

Abstract translation: 公开了一种操作量子系统的方法，其包括计算元件，包括超导材料的绝缘环，以及用作计算元件和外部世界之间的界面的半闭环。 在一个方面，该方法包括提供电信号，例如， 磁耦合到计算元件的输入环中的电流，其在计算元件中产生磁场并感测磁耦合到计算元件的输出元件的电流和/或电压的变化。 电输入信号可以是AC信号或DC信号。 计算元件与其他相邻的计算元件和/或与接口元件电磁耦合。 计算元件和/或接口元件之间的相应磁通量用作信息载体。 铁磁芯用于改善相邻元件之间的磁耦合。

公开(公告)号：US08994096B2

公开(公告)日：2015-03-31

申请号：US13124925

申请日：2009-10-22

Applicant: Dusan Golubovic

Inventor： Dusan Golubovic

IPC: H01L29/792 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/495 ,  H01L29/66833 ,  H01L29/792

Abstract: The invention relates to a multi-transistor, e.g. a two-transistor memory cell with an enhancement junction field effect transistor (JFET) as the access gate transistor. In one embodiment, the JFET is provided as a self-aligned JFET. Accordingly, and advantageous over the prior art, the invention allows for a method for manufacturing a multi-transistor, e.g. a two-transistor memory cell comprising a JFET as the access transistor without adding any additional masks and/or processing steps. Such a multi-transistor, e.g. a two-transistor memory cell according to invention, provides an improved reliability.

Abstract translation: 本发明涉及一种多晶体管，例如， 具有增强型结型场效应晶体管（JFET）作为存取栅极晶体管的双晶体管存储单元。 在一个实施例中，JFET被提供为自对准JFET。 因此，优于现有技术，本发明允许制造多晶体管的方法，例如， 包括作为存取晶体管的JFET的双晶体管存储单元，而不添加任何附加的掩模和/或处理步骤。 这样的多晶体管，例如 根据本发明的双晶体管存储单元提供了改进的可靠性。

公开(公告)号：US08546862B2

公开(公告)日：2013-10-01

申请号：US13262319

申请日：2010-04-19

Applicant: Dusan Golubovic

Inventor： Dusan Golubovic

IPC: H01L27/105 ,  H01L21/336

CPC classification number: H01L29/42332 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/42348 ,  H01L29/7881 ,  H01L29/792

Abstract: A memory cell (100) comprising a transistor, the transistor comprising a substrate (101), a first source/drain region (102), a second source/drain region (112), a gate (104) and a gate insulating layer (103) positioned between the substrate (101) and the gate (104), wherein the gate insulating layer (103) is in a direct contact with the substrate (101) and comprises charge traps (131) distributed over an entire volume of the gate insulating layer (101).

Abstract translation: 包括晶体管的存储单元（100），所述晶体管包括衬底（101），第一源极/漏极区域（102），第二源极/漏极区域（112），栅极（104）和栅极绝缘层 103）定位在所述基板（101）和所述栅极（104）之间，其中所述栅极绝缘层（103）与所述基板（101）直接接触并且包括分布在所述栅极的整个体积上的电荷阱（131） 绝缘层（101）。

公开(公告)号：US20120213466A1

公开(公告)日：2012-08-23

申请号：US13029951

申请日：2011-02-17

Applicant: Dusan Golubovic ,  Gerhard Koops ,  Tony Vanhoucke ,  Rob Van Dalen

Inventor： Dusan Golubovic ,  Gerhard Koops ,  Tony Vanhoucke ,  Rob Van Dalen

IPC: G02B6/122 ,  H01L31/18

CPC classification number: H01L27/15 ,  H01L31/173 ,  H01L33/343

Abstract: An optocoupler device facilitates on-chip galvanic isolation. In accordance with various example embodiments, an optocoupler circuit includes a silicon-on-insulator substrate having a silicon layer on a buried insulator layer, a silicon-based light-emitting diode (LED) having a silicon p-n junction in the silicon layer, and a silicon-based photodetector in the silicon layer. The LED and photodetector are respectively connected to galvanically isolated circuits in the silicon layer. A local oxidation of silicon (LOCOS) isolation material and the buried insulator layer galvanically isolate the first circuit from the second circuit to prevent charge carriers from moving between the first and second circuits. The LED and photodetector communicate optically to pass signals between the galvanically isolated circuits.

Abstract translation: 光耦合器件便于片上电流隔离。 根据各种示例实施例，光耦合器电路包括在绝缘体层上具有硅层的绝缘体上硅衬底，在硅层中具有硅pn结的硅基发光二极管（LED），以及 硅层中的硅基光电探测器。 LED和光电检测器分别连接到硅层中的电隔离电路。 硅（LOCOS）隔离材料的局部氧化和掩埋绝缘体层将第一电路与第二电路电隔离，以防止电荷载流子在第一和第二电路之间移动。 LED和光电检测器以光学方式进行通信，以在电隔离电路之间传递信号。

公开(公告)号：US08003410B2

公开(公告)日：2011-08-23

申请号：US12237822

申请日：2008-09-25

Applicant: Christoph Kerner ,  Wim Magnus ,  Dusan Golubovic

Inventor： Christoph Kerner ,  Wim Magnus ,  Dusan Golubovic

IPC: H01L21/00 ,  G11C11/44 ,  G11B11/00

CPC classification number: B82Y10/00 ,  G06N99/002 ,  G11C11/06 ,  G11C11/44 ,  Y10S505/832

Abstract: A method of operating a quantum system comprising computational elements, including an insulated ring of superconductive material, and semi-closed rings used as an interface between the computational elements and the external world, is disclosed. In one aspect, the method comprises providing an electrical signal, e.g. a current, in an input ring magnetically coupled to a computational element, which generates a magnetic field in the computational element and sensing the change in the current and/or voltage of an output element magnetically coupled to the computational element. The electrical input signal can be an AC signal or a DC signal. The computational element is electromagnetically coupled with other adjacent computational elements and/or with the interface elements. The corresponding magnetic flux between the computational elements and/or the interface elements acts as an information carrier. Ferromagnetic cores are used to improve the magnetic coupling between adjacent elements.

Abstract translation: 公开了一种操作量子系统的方法，其包括计算元件，包括超导材料的绝缘环，以及用作计算元件和外部世界之间的界面的半闭环。 在一个方面，该方法包括提供电信号，例如， 磁耦合到计算元件的输入环中的电流，其在计算元件中产生磁场并感测磁耦合到计算元件的输出元件的电流和/或电压的变化。 电输入信号可以是AC信号或DC信号。 计算元件与其他相邻的计算元件和/或与接口元件电磁耦合。 计算元件和/或接口元件之间的相应磁通量用作信息载体。 铁磁芯用于改善相邻元件之间的磁耦合。

公开(公告)号：US08963219B2

公开(公告)日：2015-02-24

申请号：US13270898

申请日：2011-10-11

Applicant: Gilberto Curatola ,  Dusan Golubovic ,  Johannes Josephus Theodorus Marinus Donkers ,  Guillaume Boccardi ,  Hans Mertens

Inventor： Gilberto Curatola ,  Dusan Golubovic ,  Johannes Josephus Theodorus Marinus Donkers ,  Guillaume Boccardi ,  Hans Mertens

IPC: H01L29/66 ,  H01L29/76 ,  H01L21/337 ,  H01L29/739 ,  B82Y10/00 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L29/7391 ,  B82Y10/00 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/66356 ,  H01L29/7613

Abstract: A tunnel field effect transistor and a method of making the same. The transistor includes a semiconductor substrate. The transistor also includes a gate located on a major surface of the substrate. The transistor further includes a drain of a first conductivity type. The transistor also includes a source of a second conductivity type extending beneath the gate. The source is separated from the gate by a channel region and a gate dielectric. The transistor is operable to allow charge carrier tunnelling from an inversion layer through an upper surface of the source.

Abstract translation: 隧道场效应晶体管及其制造方法。 晶体管包括半导体衬底。 晶体管还包括位于衬底的主表面上的栅极。 晶体管还包括第一导电类型的漏极。 晶体管还包括在栅极下延伸的第二导电类型的源。 源极通过沟道区和栅极电介质与栅极分离。 晶体管可操作以允许电荷载流子从反型层通过源的上表面穿透。

公开(公告)号：US08749223B2

公开(公告)日：2014-06-10

申请号：US13165868

申请日：2011-06-22

Applicant: Maarten Jacobus Swanenberg ,  Dusan Golubovic

Inventor： Maarten Jacobus Swanenberg ,  Dusan Golubovic

IPC: G01R19/00 ,  H01L21/331 ,  H01L21/70

CPC classification number: H01L27/0266

Abstract: Various exemplary embodiments relate to an isolation device including a semiconductor layer and an insulation layer. The insulation layer insulates a central portion of the semiconductor layer. A high voltage terminal connects to the insulation layer, a first low voltage terminal connects to a first non-insulated portion of the semiconductor layer, and a second low voltage terminal connects to a second non-insulated portion of the semiconductor layer. The first and second low voltage terminals are electrically connected via the semiconductor layer. A voltage applied to the high voltage terminal influences the conductance of the semiconductor layer. The high voltage terminal is galvanically isolated from the first and second low voltage terminals.

Abstract translation: 各种示例性实施例涉及包括半导体层和绝缘层的隔离装置。 绝缘层绝缘半导体层的中心部分。 高压端子连接到绝缘层，第一低电压端子连接到半导体层的第一非绝缘部分，第二低电压端子连接到半导体层的第二非绝缘部分。 第一和第二低压端子经由半导体层电连接。 施加到高电压端子的电压影响半导体层的电导。 高压端子与第一和第二低压端子电隔离。

公开(公告)号：US08546863B2

公开(公告)日：2013-10-01

申请号：US12594673

申请日：2008-04-17

Applicant: Almudena Huerta ,  Michiel Jos Van Duuren ,  Nader Akil ,  Dusan Golubovic ,  Mohamed Boutchich

Inventor： Almudena Huerta ,  Michiel Jos Van Duuren ,  Nader Akil ,  Dusan Golubovic ,  Mohamed Boutchich

IPC: H01L29/76 ,  H01L21/336

CPC classification number: B82Y10/00 ,  G11C16/0433 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0203 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

Abstract: A memory cell, the memory cell comprising a substrate, a nanowire extending along a vertical trench formed in the substrate, a control gate surrounding the nanowire, and a charge storage structure formed between the control gate and the nanowire.

Abstract translation: 存储单元，所述存储单元包括衬底，沿着形成在所述衬底中的垂直沟槽延伸的纳米线，围绕所述纳米线的控制栅极以及形成在所述控制栅极和所述纳米线之间的电荷存储结构。

公开(公告)号：US20120248570A1

公开(公告)日：2012-10-04

申请号：US13513834

申请日：2010-12-14

Applicant: Dusan Golubovic ,  Kyriaki Fotopoulou

Inventor： Dusan Golubovic ,  Kyriaki Fotopoulou

IPC: H01L29/82 ,  H01L21/02

CPC classification number: H01F17/0006 ,  H01F41/046 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor chip has an integrated inductor, manufactured during back end of line processing. In particular, a loop (30) is formed in a metallization layer and a central region (32) of magnetic material is provided within the loop. The size of the central region is controlled so that it includes no more than five magnetic domains to achieve the desired properties.

Abstract translation: 半导体芯片具有在线路处理后端制造的集成电感器。 特别地，在金属化层中形成环（30），并且在环内提供磁性材料的中心区域（32）。 控制中心区域的尺寸，使得其包含不超过五个磁畴以实现所需的性质。