公开(公告)号：US08749223B2

公开(公告)日：2014-06-10

申请号：US13165868

申请日：2011-06-22

Applicant: Maarten Jacobus Swanenberg ,  Dusan Golubovic

Inventor： Maarten Jacobus Swanenberg ,  Dusan Golubovic

IPC: G01R19/00 ,  H01L21/331 ,  H01L21/70

CPC classification number: H01L27/0266

Abstract: Various exemplary embodiments relate to an isolation device including a semiconductor layer and an insulation layer. The insulation layer insulates a central portion of the semiconductor layer. A high voltage terminal connects to the insulation layer, a first low voltage terminal connects to a first non-insulated portion of the semiconductor layer, and a second low voltage terminal connects to a second non-insulated portion of the semiconductor layer. The first and second low voltage terminals are electrically connected via the semiconductor layer. A voltage applied to the high voltage terminal influences the conductance of the semiconductor layer. The high voltage terminal is galvanically isolated from the first and second low voltage terminals.

Abstract translation: 各种示例性实施例涉及包括半导体层和绝缘层的隔离装置。 绝缘层绝缘半导体层的中心部分。 高压端子连接到绝缘层，第一低电压端子连接到半导体层的第一非绝缘部分，第二低电压端子连接到半导体层的第二非绝缘部分。 第一和第二低压端子经由半导体层电连接。 施加到高电压端子的电压影响半导体层的电导。 高压端子与第一和第二低压端子电隔离。

公开(公告)号：US08818265B2

公开(公告)日：2014-08-26

申请号：US13454815

申请日：2012-04-24

Applicant: Peter Gerard Steeneken ,  Maarten Jacobus Swanenberg ,  Henk Boezen ,  Gerhard Koops ,  Frans Bontekoe ,  Reinout Woltjer

Inventor： Peter Gerard Steeneken ,  Maarten Jacobus Swanenberg ,  Henk Boezen ,  Gerhard Koops ,  Frans Bontekoe ,  Reinout Woltjer

IPC: H04B5/00 ,  H01L21/70 ,  H01L29/00 ,  H01L21/02 ,  H03K17/00 ,  H04B1/44

CPC classification number: H04B1/44 ,  H03K17/00

Abstract: One or more embodiments provide circuitry for isolation and communication of signals between circuits operating in different voltage domains using capacitive coupling. The embodiments utilize capacitive structures having increased breakdown voltage in comparison to previous parallel plate implementations. The capacitive isolation is provided by parallel plate capacitive structures, each implemented to have parallel plates of different horizontal sizes. Due to the difference in horizontal size, edges of the parallel plates, where electric fields are the strongest, are laterally offset from the region where the parallel plates overlap. As a result, breakdown voltage between the parallel plates is increased.

Abstract translation: 一个或多个实施例提供用于使用电容耦合在不同电压域中工作的电路之间的信号的隔离和通信的电路。 与先前的平行板实现相比，这些实施例利用具有增加的击穿电压的电容结构。 电容隔离由平行板电容结构提供，每个电容结构被实现为具有不同水平尺寸的平行板。 由于水平尺寸的差异，电场最强的平行板的边缘与平行板重叠的区域横向偏移。 结果，平行板之间的击穿电压增加。

公开(公告)号：US20090045460A1

公开(公告)日：2009-02-19

申请号：US11577312

申请日：2005-10-13

Applicant: Jan Jacob Koning ,  Jan-Harm Nieland ,  Johannes Hendrik Hermanus Alexius Egbers ,  Maarten Jacobus Swanenberg ,  Alfred Grakist ,  Adrianus Willem Ludikhuize

Inventor： Jan Jacob Koning ,  Jan-Harm Nieland ,  Johannes Hendrik Hermanus Alexius Egbers ,  Maarten Jacobus Swanenberg ,  Alfred Grakist ,  Adrianus Willem Ludikhuize

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/7824 ,  H01L29/78609 ,  H01L29/78624

Abstract: A PMOS device comprises a semiconductor-on-insulator (SOI) substrate having a layer of insulating material over which is provided an active layer of n-type semiconductor material.P-type source and drain regions are provided by diffusion in the n-type active layer. A p-type plug is provided at the source region, which extends through the active semiconductor layer to the insulating layer. The plug is provided so as to enable the source voltage applied to the device to be lifted significantly above the substrate voltage without the occurrence of excessive leakage currents.

Abstract translation: PMOS器件包括具有绝缘材料层的绝缘体上半导体（SOI）衬底，在其上提供n型半导体材料的有源层。 P型源区和漏区由n型有源层中的扩散提供。 在源极区域设置有p型插头，其延伸穿过有源半导体层到绝缘层。 提供插头以使得施加到器件的源电压能够显着地提升到衬底电压之上，而不会发生过大的漏电流。

公开(公告)号：US07790589B2

公开(公告)日：2010-09-07

申请号：US11742404

申请日：2007-04-30

Applicant: Paulus J. T. Eggenkamp ,  Priscilla W. M. Boos ,  Maarten Jacobus Swanenberg ,  Rob Van Dalen ,  Anco Heringa ,  Adrianus Willem Ludikhuize

Inventor： Paulus J. T. Eggenkamp ,  Priscilla W. M. Boos ,  Maarten Jacobus Swanenberg ,  Rob Van Dalen ,  Anco Heringa ,  Adrianus Willem Ludikhuize

IPC: H01L21/22 ,  H01L21/38

CPC classification number: H01L29/7835 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66659

Abstract: A method of fabricating high-voltage semiconductor devices, the semiconductor devices and a mask for implanting dopants in a semiconductor are described.

Abstract translation: 描述制造高压半导体器件的方法，半导体器件和用于在半导体中注入掺杂剂的掩模。

公开(公告)号：US20130281033A1

公开(公告)日：2013-10-24

申请号：US13454815

申请日：2012-04-24

Applicant: Peter Gerard Steeneken ,  Maarten Jacobus Swanenberg ,  Henk Boezen ,  Gerhard Koops ,  Frans Bontekoe ,  Reinout Woltjer

Inventor： Peter Gerard Steeneken ,  Maarten Jacobus Swanenberg ,  Henk Boezen ,  Gerhard Koops ,  Frans Bontekoe ,  Reinout Woltjer

IPC: H04B1/44

CPC classification number: H04B1/44 ,  H03K17/00

Abstract: One or more embodiments provide circuitry for isolation and communication of signals between circuits operating in different voltage domains using capacitive coupling. The embodiments utilize capacitive structures having increased breakdown voltage in comparison to previous parallel plate implementations. The capacitive isolation is provided by parallel plate capacitive structures, each implemented to have parallel plates of different horizontal sizes. Due to the difference in horizontal size, edges of the parallel plates, where electric fields are the strongest, are laterally offset from the region where the parallel plates overlap. As a result, breakdown voltage between the parallel plates is increased.

Abstract translation: 一个或多个实施例提供用于使用电容耦合在不同电压域中工作的电路之间的信号的隔离和通信的电路。 与先前的平行板实现相比，这些实施例利用具有增加的击穿电压的电容结构。 电容隔离由平行板电容结构提供，每个电容结构被实现为具有不同水平尺寸的平行板。 由于水平尺寸的差异，电场最强的平行板的边缘与平行板重叠的区域横向偏移。 结果，平行板之间的击穿电压增加。

公开(公告)号：US20100001362A1

公开(公告)日：2010-01-07

申请号：US11914648

申请日：2006-05-22

Applicant: Rob Van Dalen ,  Maarten Jacobus Swanenberg

Inventor： Rob Van Dalen ,  Maarten Jacobus Swanenberg

IPC: H01L29/06

CPC classification number: H01L29/0634 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/404 ,  H01L29/7811 ,  H01L29/861

Abstract: A semiconductor device has active region (30) and edge termination region (32) which includes a plurality of floating field regions (46). Field plates (54) extend in the edge termination region (32) inwards from contact holes (56) towards the active region (30) over a plurality of floating field regions (46). Pillars (40) may be provided.

Abstract translation: 半导体器件具有有源区域（30）和包括多个浮动场区域（46）的边缘终止区域（32）。 场板（54）在边缘终端区域（32）中从接触孔（56）朝向有效区域（30）向内延伸穿过多个浮动场区域（46）。 可以提供支柱（40）。

公开(公告)号：US20080265319A1

公开(公告)日：2008-10-30

申请号：US11742404

申请日：2007-04-30

Applicant: Paulus J.T. Eggenkamp ,  Priscilla W.M. Boos ,  Maarten Jacobus Swanenberg ,  Rob Van Dalen ,  Anco Heringa ,  Adrianus Willem Ludikhuize

Inventor： Paulus J.T. Eggenkamp ,  Priscilla W.M. Boos ,  Maarten Jacobus Swanenberg ,  Rob Van Dalen ,  Anco Heringa ,  Adrianus Willem Ludikhuize

IPC: H01L29/78 ,  H01L21/336 ,  G03F7/00

CPC classification number: H01L29/7835 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66659

Abstract: A method of fabricating high-voltage semiconductor devices, the semiconductor devices and a mask for implanting dopants in a semiconductor are described.

Abstract translation: 描述制造高压半导体器件的方法，半导体器件和用于在半导体中注入掺杂剂的掩模。