Abstract:
One or more embodiments provide circuitry for isolation and communication of signals between circuits operating in different voltage domains using capacitive coupling. The embodiments utilize capacitive structures having increased breakdown voltage in comparison to previous parallel plate implementations. The capacitive isolation is provided by parallel plate capacitive structures, each implemented to have parallel plates of different horizontal sizes. Due to the difference in horizontal size, edges of the parallel plates, where electric fields are the strongest, are laterally offset from the region where the parallel plates overlap. As a result, breakdown voltage between the parallel plates is increased.
Abstract:
A PMOS device comprises a semiconductor-on-insulator (SOI) substrate having a layer of insulating material over which is provided an active layer of n-type semiconductor material.P-type source and drain regions are provided by diffusion in the n-type active layer. A p-type plug is provided at the source region, which extends through the active semiconductor layer to the insulating layer. The plug is provided so as to enable the source voltage applied to the device to be lifted significantly above the substrate voltage without the occurrence of excessive leakage currents.
Abstract:
Various exemplary embodiments relate to an isolation device including a semiconductor layer and an insulation layer. The insulation layer insulates a central portion of the semiconductor layer. A high voltage terminal connects to the insulation layer, a first low voltage terminal connects to a first non-insulated portion of the semiconductor layer, and a second low voltage terminal connects to a second non-insulated portion of the semiconductor layer. The first and second low voltage terminals are electrically connected via the semiconductor layer. A voltage applied to the high voltage terminal influences the conductance of the semiconductor layer. The high voltage terminal is galvanically isolated from the first and second low voltage terminals.
Abstract:
A method of fabricating high-voltage semiconductor devices, the semiconductor devices and a mask for implanting dopants in a semiconductor are described.
Abstract:
One or more embodiments provide circuitry for isolation and communication of signals between circuits operating in different voltage domains using capacitive coupling. The embodiments utilize capacitive structures having increased breakdown voltage in comparison to previous parallel plate implementations. The capacitive isolation is provided by parallel plate capacitive structures, each implemented to have parallel plates of different horizontal sizes. Due to the difference in horizontal size, edges of the parallel plates, where electric fields are the strongest, are laterally offset from the region where the parallel plates overlap. As a result, breakdown voltage between the parallel plates is increased.
Abstract:
Various exemplary embodiments relate to an isolation device including a semiconductor layer and an insulation layer. The insulation layer insulates a central portion of the semiconductor layer. A high voltage terminal connects to the insulation layer, a first low voltage terminal connects to a first non-insulated portion of the semiconductor layer, and a second low voltage terminal connects to a second non-insulated portion of the semiconductor layer. The first and second low voltage terminals are electrically connected via the semiconductor layer. A voltage applied to the high voltage terminal influences the conductance of the semiconductor layer. The high voltage terminal is galvanically isolated from the first and second low voltage terminals.
Abstract:
A semiconductor device has active region (30) and edge termination region (32) which includes a plurality of floating field regions (46). Field plates (54) extend in the edge termination region (32) inwards from contact holes (56) towards the active region (30) over a plurality of floating field regions (46). Pillars (40) may be provided.
Abstract:
A method of fabricating high-voltage semiconductor devices, the semiconductor devices and a mask for implanting dopants in a semiconductor are described.