公开(公告)号：US08952513B2

公开(公告)日：2015-02-10

申请号：US13279545

申请日：2011-10-24

Applicant: Choong-bin Yim ,  Dae-Young Choi ,  Mi-Yeon Kim ,  Ji-yong Park

Inventor： Choong-bin Yim ,  Dae-Young Choi ,  Mi-Yeon Kim ,  Ji-yong Park

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/28 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/056 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2402 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/82 ,  H01L2224/82105 ,  H01L2225/0651 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/15322 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stack type semiconductor package and a method of fabricating the stack type semiconductor package. The stack type semiconductor package includes: a lower semiconductor package including a circuit board, a semiconductor chip which is disposed on an upper surface of the circuit board, via-pads which are arrayed on the upper surface of the circuit board around the semiconductor chip, and an encapsulation layer which encapsulates the upper surface of the circuit board and has via-holes through which the via-pads are exposed; and an upper semiconductor package which is stacked on the encapsulation layer, is electrically connected to the lower semiconductor package, and comprises internal connection terminals which are formed on a lower surface of the upper semiconductor package.

Abstract translation: 堆叠型半导体封装以及叠层型半导体封装的制造方法。 叠层型半导体封装包括：下半导体封装，包括电路板，设置在电路板的上表面上的半导体芯片，排列在电路板的上表面周围的半导体芯片的通孔焊盘， 以及封装层，其封装电路板的上表面并具有通孔，通孔穿过该通孔; 并且层叠在封装层上的上半导体封装电连接到下半导体封装，并且包括形成在上半导体封装的下表面上的内部连接端子。

公开(公告)号：US20140084442A1

公开(公告)日：2014-03-27

申请号：US14019638

申请日：2013-09-06

Applicant: Jung-Do Lee ,  Tae-Woo Kang ,  Dong-Han Kim ,  Yang-Hoon Ahn ,  Jang-Woo Lee ,  Dae-Young Choi

Inventor： Jung-Do Lee ,  Tae-Woo Kang ,  Dong-Han Kim ,  Yang-Hoon Ahn ,  Jang-Woo Lee ,  Dae-Young Choi

IPC: H01L23/34

CPC classification number: H01L29/34 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/4334 ,  H01L23/49811 ,  H01L24/97 ,  H01L25/105 ,  H01L29/1033 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2225/1094 ,  H01L2924/10271 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package includes a first package board, a first semiconductor chip arranged on the first package board, a heat transfer layer arranged on the first semiconductor chip, a heat spreader arranged on the heat transfer layer, and a housing having a molding part arranged on the first package board and directly surrounding side surfaces of the first semiconductor chip and a guide wall arranged on the molding part, with the guide wall spaced apart from the heat spreader and surrounding side surfaces of the heat spreader.

Abstract translation: 一种半导体封装，包括第一封装板，布置在第一封装板上的第一半导体芯片，布置在第一半导体芯片上的传热层，布置在传热层上的散热器，以及具有布置在 所述第一封装板和所述第一半导体芯片的直接环绕的侧表面和布置在所述模制部件上的引导壁，所述引导壁与所述散热器间隔开并且所述散热器的周围侧表面。

公开(公告)号：US20110291294A1

公开(公告)日：2011-12-01

申请号：US13049377

申请日：2011-03-16

Applicant: Sang-Uk Kim ,  Jin-woo Park ,  Dae-Young Choi ,  Mi-Yeon Kim ,  Sun-Hye Lee

Inventor： Sang-Uk Kim ,  Jin-woo Park ,  Dae-Young Choi ,  Mi-Yeon Kim ,  Sun-Hye Lee

IPC: H01L23/52

CPC classification number: H01L23/147 ,  H01L23/13 ,  H01L23/49827 ,  H01L23/5385 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A multi-chip package may include a first semiconductor package, a second semiconductor package and an interposer chip. The second semiconductor package may be arranged over the first semiconductor package. The interposer chip may be interposed between the first semiconductor package and the second semiconductor package. The interposer chip may have a receiving groove configured to receive the first semiconductor package. Thus, electrical connection reliability between the first semiconductor package and the second semiconductor package may be improved under a condition that the connecting terminals may have small sizes.

Abstract translation: 多芯片封装可以包括第一半导体封装，第二半导体封装和插入器芯片。 第二半导体封装可以布置在第一半导体封装之上。 插入器芯片可以插入在第一半导体封装和第二半导体封装之间。 插入器芯片可以具有被配置为接收第一半导体封装的接收槽。 因此，在连接端子可以具有小尺寸的条件下，可以提高第一半导体封装和第二半导体封装之间的电连接可靠性。

公开(公告)号：US20110237027A1

公开(公告)日：2011-09-29

申请号：US13027511

申请日：2011-02-15

Applicant: Tae-Hun Kim ,  Jin-Woo Park ,  Dae-Young Choi ,  Mi-Yeon Kim ,  Sun-Hye Lee

Inventor： Tae-Hun Kim ,  Jin-Woo Park ,  Dae-Young Choi ,  Mi-Yeon Kim ,  Sun-Hye Lee

IPC: H01L21/50

CPC classification number: H01L23/5226 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/14 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2924/00012

Abstract: Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.

Abstract translation: 提供了一种形成封装封装的方法。 使用晶片级成型工艺形成覆盖晶片的封装。 晶片包括多个半导体芯片和穿过半导体芯片的多个通孔硅通孔（TSV）。 密封剂可以具有与TSV对齐的开口。 密封剂和半导体芯片被分割以形成多个半导体封装。 另一个半导体封装堆叠在从半导体封装中选择的一个上。 另一个半导体封装电连接到TSV。

公开(公告)号：US20110109000A1

公开(公告)日：2011-05-12

申请号：US12899859

申请日：2010-10-07

Applicant: Sang-Uk Kim ,  Hyo-Chang Ryu ,  Jin-Woo Park ,  Dae-young Choi ,  Mi-yeon Kim

Inventor： Sang-Uk Kim ,  Hyo-Chang Ryu ,  Jin-Woo Park ,  Dae-young Choi ,  Mi-yeon Kim

IPC: H01L23/28

CPC classification number: H01L23/3128 ,  H01L23/16 ,  H01L23/562 ,  H01L24/13 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/13025 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided are a semiconductor package and a method of forming the same. The semiconductor package includes a stress reliever disposed on a part (more specifically, a weak part) of a semiconductor chip. The stress reliever relieves thermal and/or physical stresses caused by a molding layer. As a result, the semiconductor chip does not suffer from the thermal and/or physical stresses.

Abstract translation: 提供半导体封装及其形成方法。 半导体封装包括设置在半导体芯片的一部分（更具体地，弱部分）上的应力消除器。 应力释放器减轻了由模制层引起的热和/或物理应力。 结果，半导体芯片不会受到热和/或物理应力的影响。

公开(公告)号：US08759959B2

公开(公告)日：2014-06-24

申请号：US13029736

申请日：2011-02-17

Applicant: Choong-Bin Yim ,  Seung-Kon Mok ,  Jin-Woo Park ,  Dae-Young Choi ,  Mi-Yeon Kim

Inventor： Choong-Bin Yim ,  Seung-Kon Mok ,  Jin-Woo Park ,  Dae-Young Choi ,  Mi-Yeon Kim

IPC: H01L23/02 ,  H01L23/48

CPC classification number: H01L25/50 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device.

Abstract translation: 半导体封装包括第一半导体封装，包括第一印刷电路板和安装在第一印刷电路板上的第一半导体器件，以及堆叠在第一半导体封装上的第二半导体封装，并且包括第二印刷电路板和第二半导体 装置安装在第二印刷电路板上。 半导体封装包括至少一个第一通孔，其通过第一半导体器件将第二半导体封装电连接到第一印刷电路板。

公开(公告)号：US08653640B2

公开(公告)日：2014-02-18

申请号：US13440817

申请日：2012-04-05

Applicant: Tae-hun Kim ,  Dae-young Choi ,  Yang-hoon Ahn ,  Sun-hye Lee

Inventor： Tae-hun Kim ,  Dae-young Choi ,  Yang-hoon Ahn ,  Sun-hye Lee

IPC: H01L23/488

CPC classification number: H01L23/49811 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13169 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45164 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45171 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/01047 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/0105 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor package apparatus includes a first semiconductor package including a first semiconductor chip, a first substrate, a first terminal, and a first signal transfer medium, and a second semiconductor package including a second semiconductor chip, a second substrate, a second terminal, and a second signal transfer medium. At least one package connecting solder ball is located between the first terminal and the second terminal. A first solder ball guide member is positioned around the first terminal of the first substrate and includes a first guide surface for guiding a shape of the package connecting solder ball.

Abstract translation: 半导体封装装置包括：第一半导体封装，包括第一半导体芯片，第一基板，第一端子和第一信号传输介质;以及第二半导体封装，包括第二半导体芯片，第二基板，第二端子和 第二信号传送介质。 至少一个连接焊球的封装位于第一端子和第二端子之间。 第一焊球引导构件围绕第一基板的第一端子定位，并且包括用于引导封装连接焊球的形状的第一引导表面。

公开(公告)号：US20120193783A1

公开(公告)日：2012-08-02

申请号：US13341125

申请日：2011-12-30

Applicant: Ji-Sun HONG ,  Dae-Young CHOI ,  Mi-Yeon KIM

Inventor： Ji-Sun HONG ,  Dae-Young CHOI ,  Mi-Yeon KIM

IPC: H01L23/498 ,  H01L23/522

CPC classification number: H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package on package is provided herein, the package on package including a first semiconductor package including a first substrate, a first semiconductor chip stacked on the first substrate, a plurality of first connection members on an upper surface of the first substrate and in a first molding material, and a plurality of via holes which respectively expose the plurality of first connection members through the first molding material; a second semiconductor package including a second substrate, a second semiconductor chip stacked on the second substrate, and a plurality of second connection members on a lower surface of the second substrate; and a plurality of connection portions including a plurality of cores and a plurality of conductive fusion layers surrounding the plurality of cores, wherein the plurality of conductive fusion layers contact the upper surface of the first substrate and the lower surface of the second substrate.

Abstract translation: 本文提供了一种封装在封装上的封装，其包装包括第一半导体封装，第一半导体封装包括第一衬底，堆叠在第一衬底上的第一半导体芯片，在第一衬底的上表面上的多个第一连接构件， 模制材料和多个通孔，其分别通过第一模塑材料暴露多个第一连接构件; 第二半导体封装，包括第二衬底，堆叠在第二衬底上的第二半导体芯片和在第二衬底的下表面上的多个第二连接构件; 以及包括多个芯的多个连接部分和围绕所述多个芯的多个导电熔融层，其中所述多个导电熔融层接触所述第一基板的上表面和所述第二基板的下表面。

公开(公告)号：US20120168917A1

公开(公告)日：2012-07-05

申请号：US13279545

申请日：2011-10-24

Applicant: Choong-bin YIM ,  Dae-Young CHOI ,  Mi-Yeon KIM ,  Ji-yong PARK

Inventor： Choong-bin YIM ,  Dae-Young CHOI ,  Mi-Yeon KIM ,  Ji-yong PARK

IPC: H01L23/495 ,  H01L23/48

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/056 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2402 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/82 ,  H01L2224/82105 ,  H01L2225/0651 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/15322 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stack type semiconductor package and a method of fabricating the stack type semiconductor package. The stack type semiconductor package includes: a lower semiconductor package including a circuit board, a semiconductor chip which is disposed on an upper surface of the circuit board, via-pads which are arrayed on the upper surface of the circuit board around the semiconductor chip, and an encapsulation layer which encapsulates the upper surface of the circuit board and has via-holes through which the via-pads are exposed; and an upper semiconductor package which is stacked on the encapsulation layer, is electrically connected to the lower semiconductor package, and comprises internal connection terminals which are formed on a lower surface of the upper semiconductor package.

Abstract translation: 堆叠型半导体封装以及叠层型半导体封装的制造方法。 叠层型半导体封装包括：下半导体封装，包括电路板，设置在电路板的上表面上的半导体芯片，排列在电路板的上表面周围的半导体芯片的通孔焊盘， 以及封装层，其封装电路板的上表面并具有通孔，通孔穿过该通孔; 并且层叠在封装层上的上半导体封装电连接到下半导体封装，并且包括形成在上半导体封装的下表面上的内部连接端子。

公开(公告)号：US20110018121A1

公开(公告)日：2011-01-27

申请号：US12805131

申请日：2010-07-14

Applicant: Jinho Lee ,  Choongbin Yim ,  Jin-woo Park ,  Dae-young Choi ,  Mi-yeon Kim

Inventor： Jinho Lee ,  Choongbin Yim ,  Jin-woo Park ,  Dae-young Choi ,  Mi-yeon Kim

IPC: H01L23/52 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1515 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package may include a substrate having first and second surfaces, the second surface including a recessed portion, a first semiconductor chip mounted on the first surface, a first ball land outside the recessed portion, a connection pad inside the recessed portion, a second chip in the recessed portion, the second semiconductor chip including a through via electrically connected to the connection pad, and a second ball land electrically connected to the through via. A semiconductor package may include a substrate having first and second surfaces, the second surface including a recessed portion, a first semiconductor chip mounted on the first surface, a first ball land outside the recessed portion, a connection pad inside the recessed portion, a second semiconductor chip in the recessed portion, the second chip including a through via electrically connected to the connection pad, and a second ball land electrically connected to the through via.

Abstract translation: 半导体封装可以包括具有第一表面和第二表面的基板，第二表面包括凹部，安装在第一表面上的第一半导体芯片，凹部外侧的第一球台面，凹部内的连接垫，第二表面 所述第二半导体芯片包括电连接到所述连接焊盘的通孔，以及电连接到所述通孔的第二焊盘。 半导体封装可以包括具有第一表面和第二表面的基板，第二表面包括凹部，安装在第一表面上的第一半导体芯片，凹部外侧的第一球台面，凹部内的连接垫，第二表面 半导体芯片，所述第二芯片包括电连接到所述连接焊盘的通孔，以及电连接到所述通孔的第二焊盘。