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    MEMORY DEVICE HAVING ERROR NOTIFICATION FUNCTION
    1.
    发明申请
    MEMORY DEVICE HAVING ERROR NOTIFICATION FUNCTION 有权
    具有错误通知功能的存储器

    公开(公告)号：US20160055056A1

    公开(公告)日：2016-02-25

    申请号：US14729656

    申请日：2015-06-03

    申请人： Jong-Pil SON ,  Chul-Woo PARK ,  Seong-Jin JANG ,  Hoi-Ju CHUNG ,  Sang-Uhn CHA

    发明人： Jong-Pil SON ,  Chul-Woo PARK ,  Seong-Jin JANG ,  Hoi-Ju CHUNG ,  Sang-Uhn CHA

    IPC分类号： G06F11/10 ,  G11C29/52

    CPC分类号： G06F11/1008 ,  G06F11/1004 ,  G06F11/1024 ,  G06F11/1068 ,  G06F11/1666 ,  G11C2029/0411

    摘要： A memory device having an error notification function includes an error correction code (ECC) engine detecting and correcting an error bit by performing an ECC operation on data of the plurality of memory cells, and an error notifying circuit configured to output an error signal according to the ECC operation. The ECC engine outputs error information corresponding to the error bit corresponding to a particular address corrected by the ECC operation. The error notifying circuit may output the error signal when the particular address is not the same as any one of existing one or more failed addresses.

    摘要翻译： 具有错误通知功能的存储装置包括通过对多个存储单元的数据执行ECC操作来检测和校正错误位的纠错码（ECC）引擎，以及错误通知电路，配置为根据 ECC操作。 ECC引擎输出与通过ECC操作校正的特定地址相对应的错误位对应的错误信息。 当特定地址与现有一个或多个故障地址中的任一个不同时，错误通知电路可以输出错误信号。

    Method of refreshing a memory device, refresh address generator and memory device
    5.
    发明授权
    Method of refreshing a memory device, refresh address generator and memory device 有权
    刷新存储器件，刷新地址发生器和存储器件的方法

    公开(公告)号：US08873324B2

    公开(公告)日：2014-10-28

    申请号：US13240049

    申请日：2011-09-22

    申请人： Chul-Woo Park ,  Joo-Sun Choi ,  Hong-Sun Hwang

    发明人： Chul-Woo Park ,  Joo-Sun Choi ,  Hong-Sun Hwang

    IPC分类号： G11C7/00

    CPC分类号： G11C11/40618 ,  G11C11/40622 ,  G11C11/408

    摘要： A refresh address is generated with a refresh period for refreshing a memory device with refresh leveraging. A respective refresh is performed on a weak cell having a first address when the refresh address is a second address instead of on a first strong cell having the second address. A respective refresh is performed on one of the first strong cell or a second strong cell having a third address when the refresh address is the third address. Address information is stored for only one of the first, second, and third addresses such that memory capacity may be reduced. In alternative aspects, a respective refresh is performed on one of a weak cell, a first strong cell, or a second strong cell depending on a flag when the refresh address is any of at least one predetermined address to result in refresh leveraging.

    摘要翻译： 生成具有刷新周期的刷新地址，以刷新刷新的存储器件。 当刷新地址是第二地址而不是具有第二地址的第一强单元时，对具有第一地址的弱小区执行相应的刷新。 当刷新地址是第三地址时，在具有第三地址的第一强单元或第二强单元之一上执行相应的刷新。 仅对第一，第二和第三地址中的一个存储地址信息，从而可以减少存储容量。 在替代方面，当刷新地址是至少一个预定地址中的任一个以导致刷新利用时，依赖于标志，在弱小区，第一强小区或第二强小区中的一个上执行相应的刷新。

    Semiconductor memory device including vertical channel transistors
    6.
    发明授权
    Semiconductor memory device including vertical channel transistors 有权
    半导体存储器件包括垂直沟道晶体管

    公开(公告)号：US08830715B2

    公开(公告)日：2014-09-09

    申请号：US13304851

    申请日：2011-11-28

    申请人： Hak-Soo Yu ,  Su-A Kim ,  Hong-Sun Hwang ,  Chul-Woo Park

    发明人： Hak-Soo Yu ,  Su-A Kim ,  Hong-Sun Hwang ,  Chul-Woo Park

    IPC分类号： G11C5/02 ,  G11C11/34 ,  H01L27/108 ,  G11C7/02 ,  G11C7/06

    CPC分类号： G11C7/02 ,  G11C7/062 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10897

    摘要： A semiconductor memory device is disclosed. The semiconductor memory device includes a memory array block, a first word line and a second word line. The memory array block includes a plurality of adjacent columns of memory cells, each column of memory cells including a plurality of consecutive memory cells having a plurality of respective consecutive cell transistors that comprise at least a first group of cell transistors and a second group of cell transistors. The first word line is disposed above the plurality of respective consecutive cell transistors and electrically connected to the first group of cell transistors, and the second word line is disposed below the plurality of respective consecutive cell transistors and electrically connected to the second group of cell transistors.

    摘要翻译： 公开了一种半导体存储器件。 半导体存储器件包括存储器阵列块，第一字线和第二字线。 存储器阵列块包括多个相邻列的存储器单元，每列存储器单元包括多个连续的存储单元，其具有多个相应的连续单元晶体管，其包括至少第一组单元晶体管和第二组单元 晶体管。 第一字线设置在多个相应的连续单元晶体管的上方并电连接到第一组单元晶体管，第二字线设置在多个相应的连续单元晶体管的下方，并电连接到第二组单元晶体管 。

    Semiconductor memory devices and semiconductor memory systems
    7.
    发明授权
    Semiconductor memory devices and semiconductor memory systems 有权
    半导体存储器件和半导体存储器系统

    公开(公告)号：US08705297B2

    公开(公告)日：2014-04-22

    申请号：US13282830

    申请日：2011-10-27

    申请人： Sua Kim ,  Chul-woo Park ,  Hong-sun Hwang ,  Hak-soo Yu

    发明人： Sua Kim ,  Chul-woo Park ,  Hong-sun Hwang ,  Hak-soo Yu

    IPC分类号： G11C7/00

    CPC分类号： G11C7/18 ,  G11C7/06 ,  G11C2207/002 ,  G11C2207/005

    摘要： A semiconductor memory device includes at least one memory cell block and at least one connection unit. The at least one memory cell block has a first region including at least one first memory cell connected to a first bit line, and a second region including at least one second memory cell connected to a second bit line. The at least one connection unit is configured to selectively connect the first bit line to a corresponding bit line sense amplifier based on a first control signal, and configured to selectively connect the second bit line to the corresponding bit line sense amplifier via a corresponding global bit line based on a second control signal.

    摘要翻译： 半导体存储器件包括至少一个存储单元块和至少一个连接单元。 所述至少一个存储单元块具有包括连接到第一位线的至少一个第一存储单元的第一区域和包括连接到第二位线的至少一个第二存储器单元的第二区域。 所述至少一个连接单元被配置为基于第一控制信号选择性地将第一位线连接到对应的位线读出放大器，并且被配置为经由对应的全局位选择性地将第二位线连接到对应的位线读出放大器 基于第二控制信号。

    Stacked memory devices
    9.
    发明授权
    Stacked memory devices 有权
    堆叠式存储器件

    公开(公告)号：US08611121B2

    公开(公告)日：2013-12-17

    申请号：US12662785

    申请日：2010-05-04

    申请人： Seung-eon Ahn ,  Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Hyun-ho Choi

    发明人： Seung-eon Ahn ,  Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Hyun-ho Choi

    IPC分类号： G11C5/02

    CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C2213/71 ,  G11C2213/72

    摘要： A stacked memory device may include a substrate, a plurality of memory groups sequentially stacked on the substrate, each memory group including at least one memory layer, a plurality of X-decoder layers, at least one of the plurality of X-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups, and a plurality of Y-decoder layers disposed alternately with the plurality of X-decoder layers, at least one of the plurality of Y-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups.

    摘要翻译： 层叠的存储器件可以包括衬底，顺序地堆叠在衬底上的多个存储器组，每个存储器组包括至少一个存储器层，多个X译码器层，所述多个X译码器层中的至少一个是 设置在所述多个存储器组中的每个相邻的两个存储器组之间，以及与所述多个X解码器层交替布置的多个Y译码器层，所述多个Y译码器层中的至少一个设置在每个相邻的两个存储器组之间 的多个存储器组。