公开(公告)号：US20200185290A1

公开(公告)日：2020-06-11

申请号：US16614765

申请日：2017-06-30

申请人： Intel Corporation

发明人： Dinesh PADMANABHAN RAMALEKSHMI THANU ,  Hemanth K. DHAVALESWARAPU ,  Venkata Suresh GUTHIKONDA ,  John J. BEATTY ,  Yonghao AN ,  Marco Aurelio CARTAS AYALA ,  Luke J. GARNER ,  Peng LI

IPC分类号： H01L23/16 ,  H01L23/367 ,  H01L25/16 ,  H01L21/52 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065

摘要： Semiconductor packages having a sealant bridge between an integrated heat spreader and a package substrate are described. In an embodiment, a semiconductor package includes a sealant bridge anchoring the integrated heat spreader to the package substrate at locations within an overhang gap laterally between a semiconductor die and a sidewall of the integrated heat spreader. The sealant bridge extends between a top wall of the integrated heat spreader and a die side component, such as a functional electronic component or a non-functional component, or a satellite chip on the package substrate. The sealant bridge modulates warpage or stress in thermal interface material joints to reduce thermal degradation of the semiconductor package.

公开(公告)号：US20200185286A1

公开(公告)日：2020-06-11

申请号：US16215372

申请日：2018-12-10

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Hsu-Nan FANG

IPC分类号： H01L23/053 ,  H01L23/31 ,  H01L23/42 ,  H01L21/52 ,  H01L21/56

摘要： A semiconductor package device includes a substrate, an electronic component, a ring frame, an encapsulant, a thermal conducting material and a lid. The electronic component is disposed on the substrate. The ring frame is disposed on the substrate and surrounds the electronic component. The encapsulant encapsulates the electronic component and a first portion of the ring frame. The encapsulant exposes a second portion of the ring frame. The encapsulant and the second portion of the ring frame define a space. The thermal conducting material is disposed in the space. The lid is disposed on the thermal conducting material and connects with the second portion of the ring frame.

公开(公告)号：US10586781B2

公开(公告)日：2020-03-10

申请号：US15373982

申请日：2016-12-09

申请人： SHINKAWA LTD.

发明人： Shigeru Hayata ,  Hiroya Yuzawa ,  Hiromi Tomiyama

IPC分类号： H01L21/28 ,  H01L23/00 ,  H01L21/52 ,  H01L21/67 ,  B23K1/00 ,  B23K3/08 ,  B23K101/40

摘要： A bonding apparatus 10 having a diagonal optical system 30, the bonding apparatus moves a capillary 24 down to a first heightwise position to calculate a position A11 of a tip end portion of the capillary 24 and a position A12 of a tip end portion of the capillary in an image on an imaging plane of the diagonal optical system 30, and similarly moves the capillary 24 down to a further lower second heightwise position to calculate a position A21 of the tip end portion of the capillary 24 and a position A22 of the tip end portion of the capillary in the image on the imaging plane. The bonding apparatus then estimates the position of the landing point of the capillary 24 on a bonding target 8 based on positional data for the four calculated positions A11, A12, A21, and A22, the first heightwise position, and the second heightwise position. With this, it is possible to use the diagonal optical system in the bonding apparatus to further improve positional accuracy in the bonding process.

公开(公告)号：US20200043818A1

公开(公告)日：2020-02-06

申请号：US16447569

申请日：2019-06-20

申请人： Mitsubishi Electric Corporation

发明人： Akitoshi SHIRAO

IPC分类号： H01L23/16 ,  H01L21/56 ,  H01L21/52 ,  H01L21/54 ,  H01L23/31 ,  H02M7/5387

摘要： A semiconductor device includes a case surrounding a region that contains semiconductor elements and wires. The case is provided with s(an integer greater than k and equal to or greater than three)-pieces of discharge paths for discharging an encapsulation member to the region. The s-pieces of discharge paths are provided so as to surround the region as seen in a plan view. The s-pieces of discharge paths are spirally provided as seen in a plan view.

公开(公告)号：US10553511B2

公开(公告)日：2020-02-04

申请号：US16433539

申请日：2019-06-06

申请人： Cubic Corporation

发明人： J. Robert Reid

IPC分类号： H01L23/13 ,  H01L23/00 ,  H01L23/055 ,  H01L21/48 ,  H01L21/52 ,  H01P3/06 ,  H01L23/66 ,  H01L23/498

摘要： Chip scale package such as a chip scale package having a chip integrated therein to provide an integrated chip scale package.

公开(公告)号：US20200035583A1

公开(公告)日：2020-01-30

申请号：US16596100

申请日：2019-10-08

申请人： Google LLC

发明人： Melanie Beauchemin ,  Madhusudan Iyengar ,  Christopher Malone ,  Gregory Imwalle

IPC分类号： H01L23/38 ,  H01L25/18 ,  H01L23/053 ,  H01L23/433 ,  H01L25/00 ,  H01L21/52 ,  H01L21/48 ,  F25B21/02

摘要： While the use of 2.5D/3D packaging technology results in a compact IC package, it also raises challenges with respect to thermal management. Integrated component packages according to the present disclosure provide a thermal management solution for 2.5D/3D IC packages that include a high-power component integrated with multiple lower-power components. The thermal solution provided by the present disclosure includes a mix of passive cooling by traditional heatsink or cold plate and active cooling by thermoelectric cooling (TEC) elements. Certain methods according to the present disclosure include controlling a temperature during normal operation in an IC package that includes a plurality of lower-power components located adjacent to a high-power component in which the high-power component generates a greater amount of heat relative to each of the lower-power components during normal operation.

公开(公告)号：US10515886B2

公开(公告)日：2019-12-24

申请号：US15810050

申请日：2017-11-11

申请人： BroadPak Corporation

发明人： Farhang Yazdani

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L21/48 ,  H01L21/52 ,  H01L23/04 ,  H01L23/31 ,  H01L23/473 ,  H01L23/00 ,  H01L23/66 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L25/10

摘要： An electronic package comprising a first substrate; a second substrate; at least one standoff substrate positioned between the first substrate and the second substrate, wherein the at least one standoff substrate is affixed to each of the first substrate and the second substrate, wherein the at least one standoff substrate forms a clearance between the first substrate and the second substrate, and wherein the at least one standoff substrate comprises an intervening plurality of through-substrate vias passing through the entire thickness of the at least one standoff substrate, and wherein a portion of the second plurality of through-substrate vias are electrically connected to a portion of the first through-substrate vias by way of a portion of the intervening through-substrate vias; and at least three electronic components located within the clearance.

公开(公告)号：US20190355632A1

公开(公告)日：2019-11-21

申请号：US16377084

申请日：2019-04-05

申请人： Fuji Electric Co., Ltd.

发明人： Katsumi TANIGUCHI

IPC分类号： H01L23/043 ,  H01L23/06 ,  H01L23/10 ,  H01L21/52

摘要： The present invention includes: a plurality of semiconductor modules on a metal base (conductor base); a first insulating bus bar and a second insulating bus bar connecting the semiconductor modules; a box-like insulating resin frame around the semiconductor modules; a first insulating layer that seals the semiconductor modules, the first insulating layer having an upper surface at a position that is lower than upper ends of terminals extending from an insulating circuit substrate of the semiconductor module inside the insulating resin frame; and second insulating layers on the first insulating layer inside the insulating resin frame, the upper ends of the terminals being buried inside the second insulating layers. Interfaces formed by the first insulating layer, second insulating layers, and sidewall parts (third insulating layer) of the insulating resin frame are arranged between the terminals and ground positions formed at the lower ends of the sidewall parts.

公开(公告)号：US10461232B2

公开(公告)日：2019-10-29

申请号：US16069556

申请日：2017-01-13

申请人： Citizen Watch Co., Ltd. ,  Citizen Electronics Co., Ltd.

发明人： Hiroo Kajiwara ,  Yuji Ogawa ,  Kenichiro Sato ,  Yuta Yaguchi

IPC分类号： H01L33/60 ,  C08L83/04 ,  H01L33/56 ,  H01L21/52 ,  C08G77/16 ,  C08G77/18 ,  H01L33/62

摘要： A condensation reaction-type die bonding agent has little liability of poor electrical connection at the electrodes. A condensation reaction-type die bonding agent for bonding an LED device provided on its surface with device electrodes having connection surfaces covered by gold, where the die bonding agent includes (A) a polysilsesquioxane solid in state at room temperature having trisiloxy units (TA) expressed by R1SiO3/2 where, R1 indicates one group selected from the group comprised of C1 to C15 alkyl groups, a phenyl group, and a benzyl group, and having hydroxyl groups, (B) a polysilsesquioxane liquid in state at room temperature having trisiloxy units (TB) expressed by R2SiO3/2 where, R2 indicates one group selected from the group comprised of C1 to C15 alkyl groups, a phenyl group, and a benzyl group, and having —OR2 where, R2 indicates one group selected from the group comprised of C1 to C15 alkyl groups, a phenyl group, and a benzyl group, and (C) a condensation reaction catalyst.

公开(公告)号：US20190326189A1

公开(公告)日：2019-10-24

申请号：US16380166

申请日：2019-04-10

申请人： SHINKO ELECTRIC INDUSTRIES CO., LTD.

发明人： Seiji Sato

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L21/52

摘要： A semiconductor device includes an interconnect substrate having a plurality of pads formed on a first surface thereof, a semiconductor chip having a plurality of electrodes formed on a circuit surface thereof, the semiconductor chip being mounted on the interconnect substrate such that the circuit surface faces the first surface, a plurality of bonding members that are made of a same material and that electrically couple the pads and the electrodes, and a resin disposed on the first surface to encapsulate the semiconductor chip and to fill a gap between the circuit surface and the first surface, wherein the semiconductor chip is mounted on the interconnect substrate such that the gap between the circuit surface and the first surface progressively increases from a first side to a second side.