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    SEMICONDUCTOR MEMORY DEVICE FOR PERFORMING BLIND PROGRAM OPERATION AND METHOD OF OPERATING THE SAME
    81.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE FOR PERFORMING BLIND PROGRAM OPERATION AND METHOD OF OPERATING THE SAME 审中-公开

    公开(公告)号：US20240212760A1

    公开(公告)日：2024-06-27

    申请号：US18344677

    申请日：2023-06-29

    Applicant: SK hynix Inc.

    Inventor： Hyun Seob SHIN ,  Dong Hun KWAK ,  Yeong Jo MUN

    IPC: G11C16/10 ,  G11C16/08 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/3459 ,  G11C16/0483

    Abstract: Provided herein may be a semiconductor memory and a method of operating the same. By the method, at least one normal program loop may be performed on a first memory cell, among a plurality of memory cells included in a page selected as a program target, having an N-th program state, among a plurality of program states, as a target program state, and at least one blind program loop may be performed on the first memory cell. While the at least one blind program loop is being performed, a target data pattern that is stored in a data latch of a first page buffer coupled to the first memory cell and that corresponds to the N-th program state may be changed to a first data pattern corresponding to a first program state that is lower than the N-th program state, and wherein N is a natural number equal to or greater than 2.

    MULTILEVEL PLATE LINE DECODING
    83.
    发明公开
    MULTILEVEL PLATE LINE DECODING 审中-公开

    公开(公告)号：US20240212758A1

    公开(公告)日：2024-06-27

    申请号：US18518051

    申请日：2023-11-22

    Applicant: Micron Technology, Inc.

    Inventor： Makoto Kitagawa

    IPC: G11C16/08 ,  G11C7/08 ,  G11C16/04

    CPC classification number: G11C16/08 ,  G11C7/08 ,  G11C16/0433

    Abstract: A variety of applications can include a memory device having memory cells that include capacitors as storage units with each capacitor having a plate coupled to a plate line. The memory device can include a plate line driver coupled to specific plate select lines of a set of multiple plate select lines. A plate line driver scheme can include transistors to provide a plate line voltage to a specific plate line and transistors to provide a system reference voltage to the specific plate line, where high state voltages and low state voltages can be applied to specific plate select lines to switch between placing the plate line voltage or the system reference voltage on the specific plate line. Plate select lines and the plate line driver scheme can be arranged to balance the number of plate select lines and device counts for the plate line drivers.

    Semiconductor memory device
    85.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US12020753B2

    公开(公告)日：2024-06-25

    申请号：US18359764

    申请日：2023-07-26

    Applicant: Kioxia Corporation

    Inventor： Naoya Tokiwa

    IPC: G11C16/16 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10

    CPC classification number: G11C16/16 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10

    Abstract: A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.

    MANAGING ALLOCATION OF BLOCKS IN A MEMORY SUB-SYSTEM
    87.
    发明公开
    MANAGING ALLOCATION OF BLOCKS IN A MEMORY SUB-SYSTEM 审中-公开

    公开(公告)号：US20240203507A1

    公开(公告)日：2024-06-20

    申请号：US18531100

    申请日：2023-12-06

    Applicant: Micron Technology, Inc.

    Inventor： Tomer Tzvi Eliash ,  Yu-Chung Lien ,  Zhengang Chen ,  Jameer Mulani

    IPC: G11C16/10 ,  G11C16/08 ,  G11C29/52

    CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C29/52

    Abstract: A processing device, operatively coupled with a memory device, performs a first programming operation on a first set of cells associated with a first wordline of a first die of the memory device. The processing device identifies, based on a first predefined value, a second wordline of a second die of the memory device, wherein the first predefined value is a shift in an index value of the first wordline of the first die of the memory device. The processing device further performs a second programming operation on a second set of cells associated with the second wordline of the second die, wherein the second wordline of the second die is associated with a different index value than the first wordline of the first die.

    MEMORY DEVICE AND OPERATING METHOD THEREOF
    90.
    发明公开
    MEMORY DEVICE AND OPERATING METHOD THEREOF 审中-公开

    公开(公告)号：US20240194274A1

    公开(公告)日：2024-06-13

    申请号：US18531872

    申请日：2023-12-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yonghyuk Choi ,  Jaeduk Yu ,  Yohan Lee

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/28

    CPC classification number: G11C16/3404 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/28

    Abstract: A memory device includes a word line area that is between a bit line and a common source line. The word line area includes a plurality of stacks. A first area includes first stacks with a first resistance value in the word line area, a second area includes second stacks with a second resistance value in the word line area, wherein the second resistance value is different from the first resistance value, a third area includes third stacks with a third resistance value that different from the first resistance value, and a processor is configured to control a recovery sequence of the first area, the second area, and the third area.

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