公开(公告)号：US20240371425A1

公开(公告)日：2024-11-07

申请号：US18649393

申请日：2024-04-29

Applicant: Micron Technology, Inc.

Inventor： Makoto Kitagawa

IPC: G11C11/22

Abstract: The present disclosure includes apparatuses, methods, and systems for compensating for voltage offset in memory. An embodiment includes a memory having an array of memory cells, and circuitry configured to sense a data state of a memory cell of the array by applying a voltage to a data line coupled to the memory cell and a plate of the memory cell, wherein the voltage applied to the plate is delayed relative to the voltage applied to the data line.

公开(公告)号：US20230368831A1

公开(公告)日：2023-11-16

申请号：US17740528

申请日：2022-05-10

Applicant: Micron Technology, Inc.

Inventor： Makoto Kitagawa ,  Daniele Vimercati

IPC: G11C11/22

CPC classification number: G11C11/2259 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275

Abstract: A method of performing a memory cell operation can include maintaining a plate voltage at a first access line of a memory cell during at least a first operation and a second operation of the memory cell. The method can further include charging a second access line to a first voltage greater than zero and greater than a threshold voltage of a selector device of the memory cell during the first operation on the memory cell. The method can further include, subsequent to the first operation, charging the second access line to a second voltage greater than the plate voltage plus the threshold voltage of the selector device to perform the second operation of the memory cell.

公开(公告)号：US11676649B2

公开(公告)日：2023-06-13

申请号：US17383090

申请日：2021-07-22

Applicant: Micron Technology, Inc.

Inventor： Makoto Kitagawa

IPC: G11C11/4076 ,  G11C11/22 ,  G11C11/4091 ,  G11C11/408

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2293 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4091

Abstract: Methods, systems, and devices for sense timing coordination are described. In some systems, to sense the logic states of memory cells, a memory device may generate an activation signal and route the activation signal over a signal line (e.g., a dummy word line) located at a memory array level of the memory device to one or more sense amplifiers. Based on receiving the activation signal, a sense amplifier may latch and determine the logic state of a corresponding memory cell. A first sense amplifier may sense a state of a first memory cell at a first time and a second sense amplifier may sense a state of a second memory cell at a second time in response to the same activation signal due to a propagation delay of the activation signal routed over the signal line (e.g., and corresponding to a propagation delay for activating a word line).

公开(公告)号：US11295812B2

公开(公告)日：2022-04-05

申请号：US16453772

申请日：2019-06-26

Applicant: Micron Technology, Inc.

Inventor： Wataru Otsuka ,  Takafumi Kunihiro ,  Tomohito Tsushima ,  Makoto Kitagawa ,  Jun Sumino

IPC: G11C13/00 ,  H01L27/10

Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.

公开(公告)号：US10438661B2

公开(公告)日：2019-10-08

申请号：US15162420

申请日：2016-05-23

Applicant: Micron Technology, Inc.

Inventor： Wataru Otsuka ,  Takafumi Kunihiro ,  Tomohito Tsushima ,  Makoto Kitagawa ,  Jun Sumino

IPC: G11C13/00 ,  H01L27/10

Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.

公开(公告)号：US09633728B2

公开(公告)日：2017-04-25

申请号：US14841028

申请日：2015-08-31

Applicant: Micron Technology, Inc.

Inventor： Makoto Kitagawa ,  Yogesh Luthra

IPC: G11C11/16 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C11/16 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0064 ,  G11C2013/0054 ,  G11C2013/0066 ,  G11C2013/0071 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/34 ,  G11C2213/55 ,  G11C2213/79

Abstract: Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory cell changing from the first memory state to the second memory state during the provision of the program signal to the memory cell to program the memory cell, and wherein the program circuitry is configured to alter the program signal as a result of the detection and to provide the altered program signal to the memory cell to continue to program the memory cell from the first memory state to the second memory state.

公开(公告)号：US20140362633A1

公开(公告)日：2014-12-11

申请号：US13914415

申请日：2013-06-10

Applicant: Micron Technology, Inc.

Inventor： Wataru Otsuka ,  Takafumi Kunihiro ,  Tomohito Tsushima ,  Makoto Kitagawa ,  Jun Sumino

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/0002 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0085 ,  G11C2013/0088 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/101

Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.

Abstract translation: 描述了存储器件和存储器操作方法。 一个示例性存储器系统包括公共导体和与公共导体耦合的多个存储单元。 存储器系统另外包括访问电路，其被配置为在第一和第二时刻之间的多个不同的时刻将不同的存储单元提供给多个不同的存储器状态之一。 访问电路还被配置为在第一和第二时刻之间将公共导体保持在对应于一个存储器状态的电压电位，以将存储器单元提供到一个存储器状态。

公开(公告)号：US20240281351A1

公开(公告)日：2024-08-22

申请号：US18442704

申请日：2024-02-15

Applicant: Micron Technology, Inc.

Inventor： Makoto Kitagawa

IPC: G06F11/273

CPC classification number: G06F11/2733

Abstract: A memory device can include an array of memory cells comprising groups of memory cells, the groups including at least one redundant group for repairing a defective group. The memory device can include a controller coupled to the array. Responsive to receiving a memory access command, the controller can detect whether a defective group is present. If a defect is present, sensing operations are not performed for the defective group. If no defect is present, sensing operations are not performed for the redundant group.

公开(公告)号：US20230113576A1

公开(公告)日：2023-04-13

申请号：US18053966

申请日：2022-11-09

Applicant: Micron Technology, Inc.

Inventor： Makoto Kitagawa

IPC: H10B53/30 ,  H10B53/40 ,  G11C11/22 ,  H01L29/786

Abstract: Methods, systems, and devices for power gating in a memory device are described for using one or more memory cells as drivers for load circuits of a memory device. A group of memory cells of the memory device may represent memory cells that include a switching component and that omit a memory storage element. These memory cells may be coupled with respective plate lines that may be coupled with a voltage source having a first supply voltage. Each memory cell of the group may also be coupled with a respective digit line that may be coupled with the load circuits. Respective switching components of the group of memory cells may therefore act as drivers to apply the first supply voltage to one or more load circuits by coupling a digit line with a plate line having the first supply voltage.

公开(公告)号：US20190318782A1

公开(公告)日：2019-10-17

申请号：US16453772

申请日：2019-06-26

Applicant: Micron Technology, Inc.

Inventor： Wataru Otsuka ,  Takafumi Kunihiro ,  Tomohito Tsushima ,  Makoto Kitagawa ,  Jun Sumino

IPC: G11C13/00

Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.