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135 条记录 (耗时 0.018 秒)

    Multiplier for processing multi-valued data
    81.
    发明授权
    Multiplier for processing multi-valued data 失效
    用于处理多值数据的乘数

    公开(公告)号：US5289399A

    公开(公告)日：1994-02-22

    申请号：US984695

    申请日：1992-12-02

    申请人： Yukihiro Yoshida

    发明人： Yukihiro Yoshida

    IPC分类号： G06F7/483 ,  G06F7/49 ,  G06F7/506 ,  G06F7/52 ,  G06F7/523 ,  G06F7/527

    CPC分类号： G06F7/533 ,  G06F7/49

    摘要： A multiplier, which is capable of processing a multiplication of multi-valued data, includes a register transforming circuit (RC) for shifting data stored and outputting a plurality of data, a multiplying circuit connected to the register transforming circuit (RC) for multiplying the outputs from the register transforming circuit (RC) and an adding circuit connected to the multiplying circuit for adding the multiplied results according to a predetermined arithmetic rule based on logic to be used. The multiplier further includes an AND circuit element connected to the adding circuit for shifting and sending out the outputs from the adding circuit. A W register is connected to the adding circuit for storing the shifted outputs from the adding circuit according to the AND circuit element, and a further AND circuit element is connected to the W register for shifting and sending out the outputs from the W register. Another AND circuit element is connected to the further AND circuit element for further shifting the outputs from the further AND circuit element. Finally, a W register is connected to the further AND circuit element for storing the shifted output from the W register.

    摘要翻译： 能够处理多值数据相乘的乘法器包括用于移位存储的数据并输出多个数据的寄存器变换电路（RC），连接到寄存器变换电路（RC）的乘法电路，用于将 来自寄存器变换电路（RC）的输出和连接到乘法电路的加法电路，用于根据要使用的逻辑的预定算术规则相加乘法结果。 乘法器还包括连接到加法电路的AND电路元件，用于从加法电路移出和发出输出。 W寄存器连接到加法电路，用于根据AND电路元件存储来自加法电路的移位输出，另一个AND电路元件连接到W寄存器，用于移位和发送W寄存器的输出。 另一AND电路元件连接到另一AND电路元件，用于进一步移位另一AND电路元件的输出。 最后，W寄存器连接到另外的AND电路元件，用于存储从W寄存器移位的输出。

    Very fast variable input multi-bit adder
    82.
    发明授权
    Very fast variable input multi-bit adder 失效
    非常快速的可变输入多位加法器

    公开(公告)号：US5210711A

    公开(公告)日：1993-05-11

    申请号：US842220

    申请日：1992-02-26

    申请人： David Rossmere ,  Patrice Capitant

    发明人： David Rossmere ,  Patrice Capitant

    IPC分类号： G06F7/38 ,  G06F7/50 ,  G06F7/506 ,  G06F7/509 ,  G06F7/527 ,  G06F7/533

    CPC分类号： G06F7/509 ,  G06F7/49921

    摘要： A method and apparatus for quickly adding at least three multi-bit binary numbers. The addition is divided into two stages. In Stage I, each of the addends are grouped into like-ordered multi-bit clusters and the corresponding clusters of the addends are added together using Programmable Read Only Memory (PROM) integrated circuits (ICs) yielding several intermediate sums. In Stage II, the intermediate sums are combined to yield a final sum using Programmable Array Logic (PAL, PAL is a trademark of Monolithic Memories, Inc.) ICs. Furthermore, the final sum is rounded in Stage I (and clipped if necessary in a third stage) before being provided as output. Clipping is achieved by setting the output sum to zero if the final sum is negative and setting the output sum to a predetermined threshold value if the final sum exceeds the threshold value.

    摘要翻译： 一种用于快速添加至少三个多位二进制数的方法和装置。 添加分为两个阶段。 在阶段I中，每个加数被分组成类似有序的多位簇，并且使用可产生几个中间和的可编程只读存储器（PROM）集成电路（IC）将相应的相应簇叠加在一起。 在阶段II中，使用可编程阵列逻辑（PAL，PAL是Monolithic Memories，Inc。的商标）IC来组合中间和以产生最终总和。 此外，最终总和在第一阶段进行四舍五入，并在作为输出提供之前（如有必要，在第三阶段中进行裁剪）。 如果最终总和为负，则将输出和设置为零，并且如果最终和超过阈值，则将输出和设置为预定阈值，则可以实现剪切。

    Functionally complete family of self-timed dynamic logic circuits
    83.
    发明授权
    Functionally complete family of self-timed dynamic logic circuits 失效
    功能完整的自定义动态逻辑电路的家族

    公开(公告)号：US5208490A

    公开(公告)日：1993-05-04

    申请号：US684720

    申请日：1991-04-12

    申请人： Jeffry D. Yetter

    发明人： Jeffry D. Yetter

    IPC分类号： G06F7/38 ,  G06F7/50 ,  G06F7/52 ,  G06F7/527 ,  G06F7/53 ,  H03K19/094 ,  H03K19/096 ,  H03K19/21

    CPC分类号： G06F7/5338 ,  G06F7/501 ,  G06F7/5016 ,  H03K19/094 ,  H03K19/0966 ,  H03K19/215 ,  G06F2207/3872

    摘要： A logic system uses novel mousetrap logic gates which implement novel vector logic. In a vector logic system, any number of valid vector logic states and one invalid vector logic state is defined by the logic signals on a set of logic paths. An invalid vector logic state is defined as the case when all logic paths exhibit a low logic signal. A valid vector logic state can be defined in a variety of ways. In the preferred embodiment, a valid vector logic state is defined as the case when one and only one of said logic paths exhibits a high logic signal. Furthermore, mousetrap logic gates, which can be connected directly in series and/or parallel to collectively perform logic functions, implement the foregoing logic scheme. Each mousetrap logic gate has an arming mechanism, ladder logic, and a buffer. A precharge is supplied by the arming mechanism to the buffer. Incoming logic is operated upon by the ladder logic and used to trigger the precharged buffer. Each of the mousetrap gates is self-timed so that no output exists until all necessary valid inputs are present.

    摘要翻译： 逻辑系统使用新颖的捕鼠器逻辑门，实现新颖的矢量逻辑。 在矢量逻辑系统中，任何数量的有效矢量逻辑状态和一个无效矢量逻辑状态由一组逻辑路径上的逻辑信号定义。 无效的向量逻辑状态被定义为当所有逻辑路径呈现低逻辑信号时的情况。 可以以多种方式定义有效的向量逻辑状态。 在优选实施例中，有效矢量逻辑状态被定义为当所述逻辑路径中的一个仅仅一个呈现高逻辑信号时的情况。 此外，可以直接串联和/或并联连接以集体执行逻辑功能的捕鼠器逻辑门实现上述逻辑方案。 每个捕鼠器逻辑门具有布防机制，梯形逻辑和缓冲器。 通过布防机制将预充电提供给缓冲器。 进位逻辑由梯形逻辑运行，用于触发预充电缓冲器。 每个捕鼠器门都是自定时的，所以在存在所有必要的有效输入之前，不存在任何输出。

    Circuit arrangement for calculating product sums
    84.
    发明授权
    Circuit arrangement for calculating product sums 失效
    用于计算产品系列的电路布置

    公开(公告)号：US5111422A

    公开(公告)日：1992-05-05

    申请号：US577394

    申请日：1990-09-04

    申请人： Manfred F. Ullrich

    发明人： Manfred F. Ullrich

    IPC分类号： G06F7/53 ,  G06F7/527 ,  G06F7/544

    CPC分类号： G06F7/5443

    摘要： By using a basic cell (g), an overall array (ga) for forming n products from pairs of multidigit binary numbers Amn, Bkn and for adding these n products is formed, with the formation and summation of all partial products being interleaved row by row. Each basic cell contains a delay unit for the A-coefficient inputs controlled by a half clock signal, an undelayed through connection for the B-coefficient input, an added fed via respective delay units with a sum input, a carry input, and a summation input, and a logic gate which combines the B-coefficient with the undelayed A-coefficients to form the partial product thereof and provides the partial product to the summation input of the adder.

    摘要翻译： 通过使用基本单元格（g），形成用于从多对二进制数Amn，Bkn对形成n个乘积的总体阵列（ga），并且用于添加这些n个乘积，并且所有部分乘积的形成和求和被交替排列 行。 每个基本单元包含用于由半时钟信号控制的A系数输入的延迟单元，用于B系数输入的不延迟的连接，通过具有和输入的相应延迟单元，进位输入和加法 输入和逻辑门，其将B系数与未延迟的A系数组合以形成其部分乘积，并将加法器的求和输入提供部分乘积。

    Generalized digital multiplier and digital filter using said multiplier
    87.
    发明授权
    Generalized digital multiplier and digital filter using said multiplier 失效
    广义数字乘法器和数字滤波器使用所述乘法器

    公开(公告)号：US4974186A

    公开(公告)日：1990-11-27

    申请号：US300884

    申请日：1989-01-24

    申请人： Pierre Duhamel ,  Zhijian Mou ,  Michel Cand

    发明人： Pierre Duhamel ,  Zhijian Mou ,  Michel Cand

    IPC分类号： G06F7/53 ,  G06F7/527 ,  G06F7/544 ,  H03H17/02 ,  H03H17/06

    CPC分类号： H03H17/0223 ,  G06F7/5443

    摘要： The multiplier according to the invention comprises N shift registers (RD.sub.O, . . . , RD.sub.N-1) containing the words x.sub.i on B bits, N conditional adders (AdC.sub.O, . . . , AdC.sub.N-1) each adding to the partial sum which they receive a constant coefficient (a.sub.1), conditional on the value of the bit (x.sub.i,j) which they receive from the associated register (RD.sub.1) and an adder accumulator (AdAc). The digital filter using such a multiplier also comprises a parallel word input register.

    摘要翻译： 根据本发明的乘法器包括N位移寄存器（RDO，...，RDN-1），其包含B位上的单词xi，N个条件加法器（AdCO，...，AdCN-1） 它们接收常数系数（a1），取决于它们从相关联寄存器（RD1）和加法器累加器（AdAc）接收的位（xi，j）的值。 使用这种乘法器的数字滤波器还包括并行字输入寄存器。

    Cordic complex multiplier
    90.
    发明授权
    Cordic complex multiplier 失效
    Cordic复数乘法器

    公开(公告)号：US4896287A

    公开(公告)日：1990-01-23

    申请号：US200491

    申请日：1988-05-31

    申请人： Matthew O'Donnell ,  William E. Engeler

    发明人： Matthew O'Donnell ,  William E. Engeler

    IPC分类号： G06F7/52 ,  G06F7/48 ,  G06F7/523 ,  G06F7/527 ,  G06F7/544 ,  G06F17/16 ,  H03C3/40

    CPC分类号： H03C3/40 ,  G06F7/4812 ,  G06F7/4818 ,  G06F7/5446

    摘要： A CORDIC (COordinate Rotation DIgital Computer) subsystem for multiplication of two complex digital numbers B and C, where one number is the sum of real and imaginary data portions, expressed in rectangular form (say C.sub.r or C.sub.I), and the other number can be expressed in the rectangular form or can be represented by magnitude data, expressed in polar form (say, .vertline.B.vertline., .phi.). An N-stage CORDIC portion of either recursive or pipeline sequential form, but devoid of multipliers, is used to rotate the I and Q terms of the first number through a phase angle .phi. of the polar-form multiplier number of the equivalent, taken from the rectangular form. The final computed data are the real and imaginary parts of the product.

    摘要翻译： 用于乘以两个复数数字B和C的CORDIC（协调旋转二进制计算机）子系统，其中一个数字是以矩形形式表示的实数据和虚数据部分的总和（例如Cr或CI），另一个数字可以是 以矩形形式表示，或者可以用以极性形式（例如| B |，phi）表示的幅度数据来表示。 使用递归或流水线顺序形式的N阶CORDIC部分，但没有乘数，用于旋转第一个数字的I和Q项，通过相当于极性形式乘数的相位角phi，取自 矩形。 最终的计算数据是产品的实部和虚部。