-
公开(公告)号:US5285406A
公开(公告)日:1994-02-08
申请号:US991082
申请日:1992-12-14
摘要: A high speed adder suitable for incorporation into electronic digital processing circuits includes at least one first independent adder assuming a carry in of zero (0); at least one second independent adder assuming a carry in of one (1); carry prediction logic circuitry for producing carries for the first and second independent adders, which carry prediction logic circuitry is operable simultaneously with the first and second independent adders; and a final mux for producing a correct result based upon outputs received from the first and second independent adders and the carry prediction logic circuitry.
摘要翻译: 一种适用于并入电子数字处理电路的高速加法器包括至少一个第一独立的加法器,假定进位为零(0); 至少一个第二独立加法器,其假设为一(1)的进位。 携带用于产生用于第一和第二独立加法器的运载的预测逻辑电路,其携带预测逻辑电路可与第一和第二独立加法器同时操作; 以及用于根据从第一和第二独立加法器和进位预测逻辑电路接收的输出产生正确结果的最终多路复用器。
-
公开(公告)号:US5095458A
公开(公告)日:1992-03-10
申请号:US503822
申请日:1990-04-02
CPC分类号: G06F7/508 , G06F7/49 , G06F2207/382
摘要: A high radix carry lookahead tree includes a plurality of tree nodes, each of the tree nodes including a carrying chain or a variation thereof, and/or a NAND gate chain or a variation thereof; and each tree node may have three or more children.
-