知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

224 records (took 0.036 seconds)

    Structure to Reduce Etching Residue
    82.
    发明申请
    Structure to Reduce Etching Residue 有权
    减少蚀刻残渣的结构

    公开(公告)号：US20120126359A1

    公开(公告)日：2012-05-24

    申请号：US12952485

    申请日：2010-11-23

    Applicant: Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Chung-Ying Yang

    Inventor： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Chung-Ying Yang

    IPC: H01L29/06 ,  H01L21/76

    CPC classification number: H01L21/31144 ,  H01L21/32139 ,  H01L23/585 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A structure for reducing partially etched materials is described. The structure includes a layout of an intersection area between two trenches. First, a large intersection area having a trapezoidal corner may be replaced with an orthogonal intersection between two trenches. The layout reduces the intersection area as well as the possibility of having partially etched materials left at the intersection area. The structure also includes an alternative way to fill the intersection area with either an un-etched small trapezoidal area or multiple un-etched square areas, so that the opening area at the intersection point is reduced and the possibility of having partially etched materials is reduced too.

    Abstract translation: 描述了用于减少部分蚀刻的材料的结构。 该结构包括两个沟槽之间的交叉区域的布局。 首先，具有梯形角的大交叉区域可以用两个沟槽之间的正交交替来代替。 布局减少了交叉区域以及在交叉区域留下部分蚀刻的材料的可能性。 该结构还包括用未蚀刻的小梯形区域或多个未蚀刻的正方形区域填充交叉区域的替代方法，使得交点处的开口面积减小，并且部分蚀刻材料的可能性降低 太。

    SEAL RING STRUCTURE IN SEMICONDUCTOR DEVICES
    83.
    发明申请
    SEAL RING STRUCTURE IN SEMICONDUCTOR DEVICES 有权
    半导体器件密封环结构

    公开(公告)号：US20110309465A1

    公开(公告)日：2011-12-22

    申请号：US12816454

    申请日：2010-06-16

    Applicant: Hsien-Wei Chen ,  Chung-Ying Yang

    Inventor： Hsien-Wei Chen ,  Chung-Ying Yang

    IPC: H01L29/06 ,  H01L21/76

    CPC classification number: H01L23/585 ,  H01L23/3157 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

    Abstract: The present disclosure provides a semiconductor device that includes a substrate having a seal ring region and a circuit region, a plurality of dummy gates disposed over the seal ring region of the substrate, and a seal ring structure disposed over the plurality of dummy gates in the seal ring region. A method of fabricating a semiconductor device is also provided, the method including providing a substrate having a seal ring region and a circuit region, forming a plurality of dummy gates over the seal ring region of the substrate, and forming a seal ring structure over the plurality of dummy gates over the seal ring region.

    Abstract translation: 本公开提供一种半导体器件，其包括具有密封环区域和电路区域的衬底，设置在衬底的密封环区域上方的多个虚拟栅极以及设置在多个虚拟栅极中的密封环结构 密封圈区域。 还提供了制造半导体器件的方法，所述方法包括提供具有密封圈区域和电路区域的衬底，在衬底的密封环区域上形成多个虚拟栅极，并在衬底上形成密封环结构 在密封圈区域上的多个虚拟门。

    Dicing Structures for Semiconductor Substrates and Methods of Fabrication Thereof
    85.
    发明申请
    Dicing Structures for Semiconductor Substrates and Methods of Fabrication Thereof 有权
    半导体基板的切割结构及其制造方法

    公开(公告)号：US20100283128A1

    公开(公告)日：2010-11-11

    申请号：US12716512

    申请日：2010-03-03

    Applicant: Hsien-Wei Chen

    Inventor： Hsien-Wei Chen

    IPC: H01L23/544 ,  H01L21/71 ,  G06F17/50

    CPC classification number: H01L23/544 ,  H01L21/32051 ,  H01L21/76811 ,  H01L21/76837 ,  H01L21/78 ,  H01L22/14 ,  H01L22/20 ,  H01L23/585 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00

    Abstract: Dicing structures for semiconductor substrates and methods of fabrication thereof are described. In one embodiment, a semiconductor wafer includes a first chip disposed in a substrate, a second chip disposed adjacent the first chip and disposed in the substrate, and a dicing street disposed between the first and the second chip. A first and a second metal level are disposed over the dicing street, wherein the second metal level is disposed above the first metal level. A first alignment mark is disposed in the first metal level above a first portion of the dicing street, and first metal features disposed in the second metal level above the first portion of the dicing street.

    Abstract translation: 描述了用于半导体衬底的切割结构及其制造方法。 在一个实施例中，半导体晶片包括设置在基板中的第一芯片，与第一芯片相邻设置并设置在基板中的第二芯片以及设置在第一芯片和第二芯片之间的切割街道。 第一和第二金属层设置在切割街道上方，其中第二金属层设置在第一金属层上方。 第一对准标记设置在切割街道的第一部分之上的第一金属层中，并且第一金属特征设置在切割街道的第一部分上方的第二金属层中。

    Scribe Line Metal Structure
    86.
    发明申请
    Scribe Line Metal Structure 有权
    划线金属结构

    公开(公告)号：US20100207251A1

    公开(公告)日：2010-08-19

    申请号：US12619464

    申请日：2009-11-16

    Applicant: Chen-Hua Yu ,  Shin-Puu Jeng ,  Hao-Yi Tsai ,  Shang-Yun Hou ,  Hsien-Wei Chen ,  Ming-Yen Chiu

    Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Hao-Yi Tsai ,  Shang-Yun Hou ,  Hsien-Wei Chen ,  Ming-Yen Chiu

    IPC: H01L23/544 ,  H01L21/00

    CPC classification number: H01L21/78

    Abstract: A system and method for preventing defaults during singulation is presented. An embodiment comprises a dummy metal structure located in the scribe region. The dummy metal structure comprises a series of alternating dummy lines that are connected through dummy vias. The dummy lines are offset from dummy lines in adjacent metal layers. Additionally, the dummy lines and dummy vias in the upper layers of the scribe line may be formed with larger dimensions than the dummy lines and dummy vias located in the lower layers.

    Abstract translation: 提出了一种在分割过程中防止违约的系统和方法。 一个实施例包括位于划线区域中的虚拟金属结构。 虚拟金属结构包括通过虚拟通孔连接的一系列交替虚拟线。 伪线与相邻金属层中的虚拟线偏移。 此外，划线的上层中的虚线和虚拟通路可以形成为具有比位于下层中的虚拟线和虚拟通孔更大的尺寸。

Patent Agency Ranking