公开(公告)号：US12147784B2

公开(公告)日：2024-11-19

申请号：US17387598

申请日：2021-07-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Hao Lee ,  Chia-Fu Lee ,  Yi-Chun Shih ,  Yu-Der Chih ,  Hidehiro Fujiwara ,  Haruki Mori ,  Wei-Chang Zhao

IPC: G06F7/544 ,  G11C11/412

Abstract: A compute-in-memory (CIM) device has a memory array with a plurality of memory cells arranged in rows and columns. The plurality of memory cells includes a first memory cell in a first row and a first column of the memory array and a second memory cell in the first row and a second column of the memory array. The first and second memory cells are configured to store respective first and second weight signals. An input driver provides a plurality of input signals. A first logic circuit is coupled to the first memory cell to provide a first output signal based on a first input signal from the input driver and the first weight signal. A second logic circuit is coupled to the second memory cell to provide a second output signal based on a second input signal from the input driver and the second weight signal.

公开(公告)号：US20240379183A1

公开(公告)日：2024-11-14

申请号：US18314825

申请日：2023-05-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Hao Lee ,  Chia-Fu Lee ,  Yu-Der Chih

IPC: G11C29/44 ,  G11C11/16

Abstract: A method for testing and repairing a memory device is provided. The memory device includes a memory array having data cells and reference cells arranged along cell rows and cell columns. The data cells are configured to store data, and the reference cells are configured to generate a reference current for reading the data stored in the data cells. The method includes: performing a row repair, to test the reference cells in each cell row, and to replace the cell row containing at least one defective reference cell by a redundant cell row comprising additional data cells and additional reference cells; and performing a local reference current trimming, to modify a ratio of an amount of the reference cells programmed with a low resistance state over an amount of the reference cells programmed with a high resistance state for at least one of the cell rows.

公开(公告)号：US20240348435A1

公开(公告)日：2024-10-17

申请号：US18624646

申请日：2024-04-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Lien Linus Lu ,  Kun-hsi Li ,  Shih-Liang Wang ,  Jonathan Tsung-Yung Chang ,  Yu-Der Chih ,  Cheng-En Lee

IPC: H04L9/08 ,  G06F7/58 ,  H04L9/32

CPC classification number: H04L9/0869 ,  G06F7/584 ,  H04L9/0877 ,  H04L9/0897 ,  H04L9/3278 ,  H04L2209/08

Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.

公开(公告)号：US12051466B2

公开(公告)日：2024-07-30

申请号：US18301745

申请日：2023-04-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Der Chih ,  Jonathan Tsung-Yung Chang ,  Yun-Sheng Chen ,  Maybe Chen ,  Ya-chin King ,  Wen Zhang Lin ,  Chrong Jung Lin ,  Hsin-Yuan Yu

IPC: G11C11/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: G11C13/004 ,  G11C13/0069 ,  H10B63/30 ,  H10N70/253 ,  G11C2013/0045 ,  G11C2013/0078

Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.

公开(公告)号：US12027205B2

公开(公告)日：2024-07-02

申请号：US17828979

申请日：2022-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zheng-Jun Lin ,  Chung-Cheng Chou ,  Yu-Der Chih

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0026 ,  G11C13/0033 ,  G11C2213/79

Abstract: A memory device includes RRAM memory cells configured to form a zero-transistor and one-resistor (0T1R) array structure in which access transistors of the RRAM memory cells are bypassed or removed. Alternatively, the access transistors of the RRAM memory cells may be arranged in a parallel structure to reduce associated IR drop and thus enable reduced write voltage operation.

公开(公告)号：US11915752B2

公开(公告)日：2024-02-27

申请号：US17709662

申请日：2022-03-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Der Chih ,  Chung-Cheng Chou ,  Chun-Yun Wu ,  Chen-Ming Hung

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0064

Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.

公开(公告)号：US20240029791A1

公开(公告)日：2024-01-25

申请号：US18352127

申请日：2023-07-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hiroki Noguchi ,  Yu-Der Chih ,  Yih Wang

IPC: G11C13/00 ,  G11C11/22 ,  G11C11/16

CPC classification number: G11C13/0069 ,  G11C11/2275 ,  G11C11/1675 ,  G11C2013/0092

Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.

公开(公告)号：US20230207005A1

公开(公告)日：2023-06-29

申请号：US17828979

申请日：2022-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zheng-Jun Lin ,  Chung-Cheng Chou ,  Yu-Der Chih

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0026 ,  G11C13/0033 ,  G11C2213/79

Abstract: A memory device includes RRAM memory cells configured to form a zero-transistor and one-resistor (0T1R) array structure in which access transistors of the RRAM memory cells are bypassed or removed. Alternatively, the access transistors of the RRAM memory cells may be arranged in a parallel structure to reduce associated IR drop and thus enable reduced write voltage operation.

公开(公告)号：US11646079B2

公开(公告)日：2023-05-09

申请号：US17337781

申请日：2021-06-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Der Chih ,  Maybe Chen ,  Yun-Sheng Chen ,  Wen Zhang Lin ,  Jonathan Tsung-Yung Chang ,  Chrong Jung Lin ,  Ya-Chin King ,  Hsin-Yuan Yu

IPC: G11C11/00 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/004 ,  G11C13/0069 ,  H01L27/2436 ,  H01L45/1206 ,  G11C2013/0045 ,  G11C2013/0078

Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.

公开(公告)号：US20220406386A1

公开(公告)日：2022-12-22

申请号：US17585031

申请日：2022-01-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Chieh Chen ,  Cheng-Hsiung Kuo ,  Yu-Der Chih

IPC: G11C16/28

Abstract: A sense amplifier control system includes a precharge control switch configured to receive a precharge signal. A reference cell is configured to receive a reference word line signal. In a precharge phase, the control switch is controlled in response to the precharge signal to precharge the reference input node to a predetermined precharge level. In a sensing phase subsequent to the pre-charge phase, the trigger circuit is configured to output a triggering signal at the output terminal in response to the reference input node reaching a triggering level.