公开(公告)号：US20180197771A1

公开(公告)日：2018-07-12

申请号：US15911617

申请日：2018-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L29/785

Abstract: A semiconductor device structure includes a first metal layer formed over a substrate and an interconnect structure formed over the first metal layer. The interconnect structure includes an upper portion, a middle portion and a lower portion, the middle portion is connected between the upper portion and the lower portion. The upper portion and the lower portion each have a constant width, and the middle portion has a tapered width which is gradually tapered from the upper portion to the lower portion.

公开(公告)号：US20180182866A1

公开(公告)日：2018-06-28

申请号：US15900748

申请日：2018-02-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/02 ,  H01L21/764 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/02271 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/515 ,  H01L29/66545 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor fin on the semiconductor substrate and a fin isolation structure on the semiconductor substrate. The fin isolation structure has an air gap dividing the semiconductor fin into two portions of the semiconductor fin, in which the air gap extends into the semiconductor substrate for a distance. The fin isolation structure includes a dielectric cap layer capping a top of the air gap, in which the dielectric cap layer is spaced apart from a bottom of the air gap.

公开(公告)号：US20180138077A1

公开(公告)日：2018-05-17

申请号：US15851661

申请日：2017-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/485

CPC classification number: H01L21/7685 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1026 ,  H01L2221/1031

Abstract: A method includes depositing a first dielectric structure over a non-insulator structure, removing a portion of the first dielectric structure to form a via opening, filling the via opening with a dummy structure, depositing a second dielectric structure over the dummy structure, etching a portion of the second dielectric structure to form a trench over the dummy structure, removing the dummy structure from the via opening, and filling the trench opening and the via opening with a conductive structure, wherein the conductive structure is electrically connected to the non-insulator structure.

公开(公告)号：US20180069101A1

公开(公告)日：2018-03-08

申请号：US15804787

申请日：2017-11-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L29/423 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/785

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a fin structure formed over the substrate. The semiconductor structure further includes an isolation structure formed around the fin structure and a gate structure formed across the fin structure. In addition, the gate structure includes a first portion formed over the fin structure and a second portion formed over the isolation structure, and the second portion of the gate structure includes an extending portion extending into the isolation structure.

公开(公告)号：US20170317178A1

公开(公告)日：2017-11-02

申请号：US15652176

申请日：2017-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Horng-Huei TSENG

IPC: H01L29/417 ,  H01L21/311 ,  H01L29/40

CPC classification number: H01L29/4991 ,  H01L21/31111 ,  H01L21/7682 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/515 ,  H01L2221/1042 ,  H01L2221/1063

Abstract: A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a gate structure and a source drain structure. A recess is formed at least partially in the first dielectric layer. A protection layer is formed at least on a sidewall of the recess. The recess is deepened to expose the source drain structure. A bottom conductor is formed in the recess and is electrically connected to the source drain structure. The protection layer is removed to form a gap between the bottom conductor and the sidewall of the recess.

公开(公告)号：US20170243869A1

公开(公告)日：2017-08-24

申请号：US15135476

申请日：2016-04-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Horng-Huei TSENG

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A semiconductor device includes a semiconductor substrate and at least one gate stack. The gate stack is present on the semiconductor substrate, and the gate stack includes at least one work function conductor and a filling conductor. The work function conductor has a recess therein. The filling conductor includes a plug portion and a cap portion. The plug portion is present in the recess of the work function conductor. The cap portion caps the work function conductor.

公开(公告)号：US20170221812A1

公开(公告)日：2017-08-03

申请号：US15131608

申请日：2016-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Horng-Huei TSENG

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76804 ,  H01L21/76832 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/5329

Abstract: An interconnection structure includes a non-insulator structure, a liner layer, a dielectric structure and a conductive structure. The liner layer is present on the non-insulator structure and has an opening therein. The dielectric structure is present on the liner layer. The dielectric structure includes a via opening therein. The conductive structure is present in the via opening of the dielectric structure and electrically connected to the non-insulator structure through the opening of the liner layer. At least a portion of the conductive structure tapers along a direction from the non-insulator structure to the dielectric structure.

公开(公告)号：US20170207337A1

公开(公告)日：2017-07-20

申请号：US15467643

申请日：2017-03-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/78 ,  H01L29/417 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/28247 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming spacer elements over sidewalls of the dummy gate stack. The method also includes removing the dummy gate stack to form a recess between the spacer elements and partially removing the spacer elements such that an upper portion of the recess becomes wider. The method further includes forming a metal gate stack in the recess and forming a protection element in the recess to cover the metal gate stack.

公开(公告)号：US20170194441A1

公开(公告)日：2017-07-06

申请号：US15417115

申请日：2017-01-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Horng-Huei TSENG

IPC: H01L29/417 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/02068 ,  H01L21/30604 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A FinFET includes a fin structure on a substrate; a dielectric layer provided on the fin structure; a metal gate crossing over the dielectric layer; two spacers respectively crossing over the dielectric layer abutting two opposite sidewalls of the metal gate, each of the two spacers having a length along a direction parallel to a longitudinal axis of the fin structure; and a source and a drain. Each of the source and the drain having a first portion peripherally enclosed by the dielectric layer, and a second portion peripherally enclosed by the two spacers, in which the length of each of the two spacers is greater than a length of the second portion, and a length of a combination of the first portion and the second portion is greater than the length of each of the two spacers.

公开(公告)号：US20170148885A1

公开(公告)日：2017-05-25

申请号：US15051595

申请日：2016-02-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Horng-Huei TSENG

IPC: H01L29/417 ,  H01L29/40

CPC classification number: H01L29/41775 ,  H01L21/28512 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/66628 ,  H01L29/7848

Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one conductor, and at least one protection layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductor is electrically connected to the source drain structure. The protection layer is present between the conductor and the first spacer and on a top surface of the first gate structure.