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公开(公告)号:US11476272B2
公开(公告)日:2022-10-18
申请号:US16227374
申请日:2018-12-20
发明人: Peter Rabkin , Masaaki Higashitani
IPC分类号: H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11529 , H01L27/11556 , H01L27/11524 , H01L27/11558 , H01L27/11519 , H01L29/792 , H01L29/16
摘要: Memory stack structures extending through an alternating stack of insulating layers and electrically conductive layers is formed over a substrate. Each memory stack structure includes a memory film and a vertical semiconductor channel. A sacrificial polycrystalline metal layer may be formed on each memory film, and a carbon precursor may be decomposed on a physically exposed surface of the sacrificial polycrystalline metal layer to generate adsorbed carbon atoms. A subset of the adsorbed carbon atoms diffuses through grain boundaries in the polycrystalline e metal layer to an interface with the memory film. The carbon atoms at the interface may be coalesced into at least one graphene layer by an anneal process. The at least one graphene layer functions as a vertical semiconductor channel, which provides a higher mobility than silicon. A metallic drain region may be formed at an upper end of each vertical semiconductor channel.
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82.
公开(公告)号:US11362079B2
公开(公告)日:2022-06-14
申请号:US16440183
申请日:2019-06-13
发明人: Chen Wu , Peter Rabkin , Masaaki Higashitani
IPC分类号: H01L25/18 , H01L23/48 , H01L23/00 , H01L25/00 , H01L23/528 , H01L21/762 , H01L21/304 , H01L21/306 , H01L21/768 , H01L27/11551
摘要: A method of forming a bonded assembly includes providing a first semiconductor die containing a first substrate, first semiconductor devices, first dielectric material layers overlying the first semiconductor devices, and first metal interconnect structures, providing a second semiconductor die containing a second substrate, second semiconductor devices, second dielectric material layers overlying the second semiconductor devices, and second metal interconnect structures, depositing a manganese layer on a top surface of the first dielectric material layers, disposing the second semiconductor die on the manganese layer such that a surface of the second dielectric material layers contacts the manganese layer, and performing a bonding anneal to bond the first semiconductor die to the second semiconductor die and to convert the manganese layer into a manganese-containing oxide layer, such that the manganese-containing oxide layer is bonded to the first dielectric material layers and the second dielectric material layers.
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公开(公告)号:US11355486B2
公开(公告)日:2022-06-07
申请号:US17062988
申请日:2020-10-05
发明人: Yuki Mizutani , Masaaki Higashitani , James Kai
IPC分类号: H01L25/18 , H01L27/11556 , H01L27/11582 , H01L25/065 , H01L23/00 , H01L25/00
摘要: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A source power supply network can be formed on the backside of the source layer.
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公开(公告)号:US11177284B2
公开(公告)日:2021-11-16
申请号:US16798643
申请日:2020-02-24
发明人: Peter Rabkin , Masaaki Higashitani , Alan Kalitsov
IPC分类号: H01L27/11597 , H01L21/02 , H01L21/306 , H01L29/778
摘要: A ferroelectric memory device includes a two-dimensional electron gas channel, a gate electrode, and a ferroelectric element located between the gate electrode and the two-dimensional electron gas channel.
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公开(公告)号:US20210174881A1
公开(公告)日:2021-06-10
申请号:US17173023
申请日:2021-02-10
摘要: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.
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公开(公告)号:US11004773B2
公开(公告)日:2021-05-11
申请号:US16391632
申请日:2019-04-23
发明人: Chen Wu , Peter Rabkin , Masaaki Higashitani
IPC分类号: H01L23/48 , H01L23/528 , H01L23/532 , H01L23/00 , H01L25/18 , H01L21/02 , H01L21/768 , H01L21/311 , H01L25/00 , H01L27/11556 , H01L27/11521 , H01L27/11526 , H01L27/11568 , H01L27/11573 , H01L27/11582 , H01L23/522 , H01L21/321 , H01L21/3105
摘要: First semiconductor devices, a first dielectric material layer, a porous dielectric material layer, and a metal interconnect structure formed within a second dielectric material layer are formed on a front-side surface of a first semiconductor substrate. A via cavity extending through the first semiconductor substrate and the first dielectric material layer are formed. The via cavity stops on the porous dielectric material layer. A continuous network of pores that are free of any solid material therein continuously extends from a bottom of the via cavity to a surface of the metal interconnect structure. A through-substrate via structure is formed in the via cavity. The through-substrate via structure includes a porous metallic material portion filling the continuous network of pores and contacting surface portions of the metal interconnect structure. Etch damage to the first semiconductor devices and metallic particle generation may be minimized by using the porous metallic material portion.
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公开(公告)号:US10910064B2
公开(公告)日:2021-02-02
申请号:US16400280
申请日:2019-05-01
发明人: Peter Rabkin , Kwang-Ho Kim , Masaaki Higashitani
IPC分类号: G11C16/24 , G11C16/04 , G11C16/32 , G11C16/34 , G11C16/08 , G11C16/14 , H01L27/11582 , H01L27/11556
摘要: An apparatus comprising strings of non-volatile memory cells, a first set of pathways connected to the strings, and a second set of pathways connected to the strings. The first set of pathways have first impedances that depend on location of respective strings. The second set of pathways having second impedances. The apparatus also includes one or more control circuits configured to compensate for location dependent impedance mismatch between the first set of pathways and the second set of pathways during memory operations on the non-volatile memory cells.
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公开(公告)号:US20200321061A1
公开(公告)日:2020-10-08
申请号:US16909830
申请日:2020-06-23
发明人: Dae Wung Kang , Peter Rabkin , Masaaki Higashitani
IPC分类号: G11C16/26 , G11C7/04 , G11C16/04 , G11C11/4074 , G11C11/56
摘要: Methods and systems for improving the reliability of data stored within a semiconductor memory over a wide range of operating temperatures are described. The amount of shifting in the threshold voltages of memory cell transistors over temperature may depend on the location of the memory cell transistors within a NAND string. To compensate for these variations, the threshold voltages of memory cell transistors in the middle of the NAND string or associated with a range of word lines between the ends of the NAND string may be adjusted by increasing the word line voltages biasing memory cell transistors on the drain-side of the selected word line when the read temperature is greater than a first threshold temperature and/or decreasing the word line voltages biasing memory cell transistors on the source-side of the selected word line when the read temperature is less than a second threshold temperature.
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89.
公开(公告)号:US20200294910A1
公开(公告)日:2020-09-17
申请号:US16886702
申请日:2020-05-28
IPC分类号: H01L23/522 , H01L23/528 , H01L23/00 , H01L49/02 , H01L27/11582
摘要: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.
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公开(公告)号:US20200013795A1
公开(公告)日:2020-01-09
申请号:US16141149
申请日:2018-09-25
发明人: Mohan Dunga , James Kai , Venkatesh P. Ramachandra , Piyush Dak , Luisa Lin , Masaaki Higashitani
IPC分类号: H01L27/11582 , H01L27/11573 , H01L27/1157 , G11C16/10 , G11C16/28 , G11C7/10
摘要: A non-volatile storage apparatus comprises a non-volatile memory structure and an I/O interface. A portion of the memory die is used as a pool capacitor for the I/O interface.
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