公开(公告)号：US20220181433A1

公开(公告)日：2022-06-09

申请号：US17116315

申请日：2020-12-09

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Chia-Ching Lin ,  Kaan Oguz ,  I-Cheng Tung ,  Uygar E. Avci ,  Matthew V. Metz ,  Ashish Verma Penumatcha ,  Ian A. Young ,  Arnab Sen Gupta

IPC: H01L49/02

Abstract: Disclosed herein are capacitors including built-in electric fields, as well as related devices and assemblies. In some embodiments, a capacitor may include a top electrode region, a bottom electrode region, and a dielectric region between and in contact with the top electrode region and the bottom electrode region, wherein the dielectric region includes a perovskite material, and the top electrode region has a different material structure than the bottom electrode region.

公开(公告)号：US20220123151A1

公开(公告)日：2022-04-21

申请号：US17551899

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： Uygar E. Avci ,  Joshua M. Howard ,  Seiyon Kim ,  Ian A. Young

IPC: H01L29/78 ,  H01L49/02 ,  H01L29/51

Abstract: Described is an apparatus which comprises: a first layer comprising a semiconductor; a second layer comprising an insulating material, the second layer adjacent to the first layer; a third layer comprising a high-k insulating material, the third layer adjacent to the second layer; a fourth layer comprising a ferroelectric material, the fourth layer adjacent to the third layer; and a fifth layer comprising a high-k insulating material, the fifth layer adjacent to the fourth layer.

公开(公告)号：US20220069009A1

公开(公告)日：2022-03-03

申请号：US17399530

申请日：2021-08-11

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/10 ,  H01L43/02

Abstract: A three dimensional (3D) array of magnetic random access memory (MRAM) bit-cells is described, wherein the array includes a mesh of: a first interconnect extending along a first axis; a second interconnect extending along a second axis; and a third interconnect extending along a third axis, wherein the first, second and third axes are orthogonal to one another, and wherein a bit-cell of the MRAM bit-cells includes: a magnetic junction device including a first electrode coupled to the first interconnect; a piezoelectric (PZe) layer adjacent to a second electrode, wherein the second electrode is coupled to the second interconnect; and a first layer adjacent to the PZe layer and the magnetic junction, wherein the first layer is coupled the third interconnect.

公开(公告)号：US11239361B2

公开(公告)日：2022-02-01

申请号：US16640043

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Uygar E. Avci ,  Joshua M. Howard ,  Seiyon Kim ,  Ian A. Young

IPC: H01L29/78 ,  H01L49/02 ,  H01L29/51

Abstract: Described is an apparatus which comprises: a first layer comprising a semiconductor; a second layer comprising an insulating material, the second layer adjacent to the first layer; a third layer comprising a high-k insulating material, the third layer adjacent to the second layer; a fourth layer comprising a ferroelectric material, the fourth layer adjacent to the third layer; and a fifth layer comprising a high-k insulating material, the fifth layer adjacent to the fourth layer.

公开(公告)号：US11069609B2

公开(公告)日：2021-07-20

申请号：US16647691

申请日：2017-11-03

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Jasmeet S. Chawla ,  Chia-Ching Lin ,  Dmitri E. Nikonov ,  Ian A. Young ,  Robert L. Bristol

IPC: H01L23/522 ,  H01F10/32 ,  H01L21/768 ,  H01L23/528 ,  H01L27/22 ,  H01L43/02

Abstract: Techniques are disclosed for forming vias for integrated circuit structures. During an additive via formation process, a dielectric material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is desired to have vias, openings are etched in the dielectric material through the removed regions, and the openings are filled with a first via material. This is then repeated for a second via material. During the subtractive via formation process, a first via material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is not desired to have vias, openings are etched in the first via material through the removed regions. This is then repeated for a second via material.

公开(公告)号：US10748603B2

公开(公告)日：2020-08-18

申请号：US16146473

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

IPC: G11C8/00 ,  G11C11/418 ,  G06F9/30 ,  G11C11/419 ,  G11C13/00 ,  G11C7/10 ,  G11C11/54 ,  G06N3/063 ,  G06N3/08 ,  G11C7/18 ,  G06F7/544 ,  G11C11/16

Abstract: A memory circuit has compute-in-memory circuitry that enables a multiply-accumulate (MAC) operation based on shared charge. Row access circuitry drives multiple rows of a memory array to multiply a first data word with a second data word stored in the memory array. The row access circuitry drives the multiple rows based on the bit pattern of the first data word. Column access circuitry drives a column of the memory array when the rows are driven. Accessed rows discharge the column line in an accumulative fashion. Sensing circuitry can sense voltage on the column line. A processor in the memory circuit computes a MAC value based on the voltage sensed on the column.

公开(公告)号：US20200235110A1

公开(公告)日：2020-07-23

申请号：US16640041

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L27/11507 ,  H01L49/02 ,  G11C11/22

Abstract: Described is an apparatus which comprises: a word line; a source line; a bit-line; and a memory bit-cell coupled to the source line, the bit-line, and the word line, wherein the memory bit-cell comprises a capacitor including ferroelectric material and a transistor fabricated on a backend of a die.

公开(公告)号：US10720438B2

公开(公告)日：2020-07-21

申请号：US16146835

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L27/11507 ,  H01L49/02 ,  H01L29/78 ,  H01L25/18 ,  H01L25/065 ,  H01L23/367 ,  H01L23/00 ,  H01L23/16

Abstract: An embodiment includes a system comprising: first, second, and third word lines on a semiconductor material; first, second, and third channels; first, second, and third capacitors including a ferroelectric material; a bit line; first, second, third, fourth, and fifth semiconductor nodes, wherein the first semiconductor node couples the first capacitor to the first channel, the second semiconductor node couples the bit line to the first channel; the third semiconductor node couples the second capacitor to the second channel, the fourth semiconductor node couples the third capacitor to the third channel, and the fifth semiconductor node couples the bit line to the third channel; wherein the first channel has a long axis and a short axis; wherein the long axis intersects a continuous, uninterrupted portion of the semiconductor material from the first channel to the third channel.

公开(公告)号：US20200152781A1

公开(公告)日：2020-05-14

申请号：US16631059

申请日：2017-09-12

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Uygar E. Avci ,  Christopher J. Wiegand ,  Anurag Chaudhry ,  Jasmeet S. Chawla ,  Ian A. Young

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/49 ,  H01L29/08 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L29/417

Abstract: Techniques are disclosed for forming semiconductor integrated circuits including one or more of source and drain contacts and gate electrodes comprising crystalline alloys including a transition metal. The crystalline alloys help to reduce contact resistance to the semiconductor devices. In some embodiments of the present disclosure, this reduction in contact resistance is accomplished by aligning the work function of the crystalline alloy with the work function of the source and drain regions such that a Schottky barrier height associated with an interface between the crystalline alloys and the source and drain regions is in a range of 0.3 eV or less.

公开(公告)号：US20200105771A1

公开(公告)日：2020-04-02

申请号：US16146835

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L27/11507 ,  H01L49/02 ,  H01L29/78 ,  H01L25/18 ,  H01L25/065 ,  H01L23/16 ,  H01L23/367 ,  H01L23/00

Abstract: An embodiment includes a system comprising: first, second, and third word lines on a semiconductor material; first, second, and third channels; first, second, and third capacitors including a ferroelectric material; a bit line; first, second, third, fourth, and fifth semiconductor nodes, wherein the first semiconductor node couples the first capacitor to the first channel, the second semiconductor node couples the bit line to the first channel; the third semiconductor node couples the second capacitor to the second channel, the fourth semiconductor node couples the third capacitor to the third channel, and the fifth semiconductor node couples the bit line to the third channel; wherein the first channel has a long axis and a short axis; wherein the long axis intersects a continuous, uninterrupted portion of the semiconductor material from the first channel to the third channel.