公开(公告)号：US20180175002A1

公开(公告)日：2018-06-21

申请号：US15380669

申请日：2016-12-15

Applicant: Intel Corporation

Inventor： Howe Yin Loo ,  Eng Huat Goh ,  Min Suet Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Khang Choong Yong

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652

Abstract: A system-in-package apparatus includes a package substrate configured to carry at least one semiconductive device on a die side and a package bottom interposer disposed on the package substrate on a land side. A land side board mates with the package bottom interposer, and enough vertical space is created by the package bottom interposer to allow space for at least one device disposed on the package substrate on the land side.

公开(公告)号：US20180145051A1

公开(公告)日：2018-05-24

申请号：US15357233

申请日：2016-11-21

Applicant: Intel Corporation

Inventor： Howe Yin Loo ,  Eng Huat Goh ,  Min Suet Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Khang Choong Yong

IPC: H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L23/498 ,  H05K1/11 ,  H05K3/36 ,  H05K3/30

CPC classification number: H01L25/0657 ,  H01L23/49811 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H05K1/111 ,  H05K1/141 ,  H05K3/30 ,  H05K3/36 ,  H05K3/368 ,  H05K2201/042 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10159 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10734

Abstract: A system-in-package apparatus includes a package substrate configured to carry at least one semiconductive device on a die side and a through-mold via package bottom interposer disposed on the package substrate on a land side. A land side board mates with the through-mold via package bottom interposer, and enough vertical space is created by the through-mold via package bottom interposer to allow space for at least one device disposed on the package substrate on the land side.

公开(公告)号：US09893444B2

公开(公告)日：2018-02-13

申请号：US14863974

申请日：2015-09-24

Applicant: INTEL CORPORATION

Inventor： Jackson Chung Peng Kong ,  Eng Huat Goh ,  Bok Eng Cheah ,  Su Sin Florence Phun ,  Khang Choong Yong ,  Min Keen Tang

IPC: H01R12/73 ,  H01R12/72 ,  C25D7/00 ,  C25D5/34 ,  C25D5/48 ,  H01R13/66 ,  H05K3/00 ,  H01G4/06 ,  H01G4/228 ,  H01G4/40

CPC classification number: H01R12/721 ,  C23C18/1653 ,  C25D5/34 ,  C25D5/48 ,  C25D7/00 ,  H01G4/06 ,  H01G4/228 ,  H01G4/40 ,  H01R12/732 ,  H01R13/6625 ,  H05K1/117 ,  H05K1/162 ,  H05K3/00 ,  H05K2201/0187

Abstract: A board-edge interconnection module features integrated capacitive coupling, which enables a board design employing the module to avoid having AC capacitors and flexible cables with bulky connectors. The recovered real estate enables further miniaturization, enabling the component to be used on a wide variety of devices, including ultra-mobile computing devices.

公开(公告)号：US09613920B2

公开(公告)日：2017-04-04

申请号：US14986542

申请日：2015-12-31

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Hoay Tien Teoh

IPC: H01L23/00 ,  H01L21/50 ,  H01L23/48 ,  H01L23/29 ,  H01L23/538 ,  H01L21/768 ,  H01L23/31

CPC classification number: H01L24/02 ,  H01L21/50 ,  H01L21/76898 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05024 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/2518 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/0105 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes.

公开(公告)号：US20240234234A9

公开(公告)日：2024-07-11

申请号：US17972923

申请日：2022-10-25

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Telesphor Kamgaing ,  Ilan Ronen ,  Kavitha Nagarajan ,  Chee Kheong Yoon ,  Chu Aun Lim ,  Eng Huat Goh ,  Jooi Wah Wong

IPC: H01L23/367 ,  H01L23/42 ,  H01L23/532

CPC classification number: H01L23/367 ,  H01L23/42 ,  H01L23/53233

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. In this arrangement, heat can become trapped inside the device. Metal fill, such as copper, is formed within a portion of the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices and towards a heat spreader.

公开(公告)号：US20240136279A1

公开(公告)日：2024-04-25

申请号：US17972975

申请日：2022-10-24

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Telesphor Kamgaing ,  Chee Kheong Yoon ,  Chu Aun Lim ,  Eng Huat Goh ,  Jooi Wah Wong ,  Kavitha Nagarajan

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L28/10

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device, and integrated inductors formed over the semiconductor devices. Power delivery to the device is on the opposite side of the semiconductor devices. The integrated inductors may be used for power step-down to reduce device thickness and/or a number of power rails.

公开(公告)号：US20240136243A1

公开(公告)日：2024-04-25

申请号：US17972923

申请日：2022-10-24

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Telesphor Kamgaing ,  Ilan Ronen ,  Kavitha Nagarajan ,  Chee Kheong Yoon ,  Chu Aun Lim ,  Eng Huat Goh ,  Jooi Wah Wong

IPC: H01L23/367 ,  H01L23/42 ,  H01L23/532

CPC classification number: H01L23/367 ,  H01L23/42 ,  H01L23/53233

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. In this arrangement, heat can become trapped inside the device. Metal fill, such as copper, is formed within a portion of the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices and towards a heat spreader.

公开(公告)号：US11823994B2

公开(公告)日：2023-11-21

申请号：US17671478

申请日：2022-02-14

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/50 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L23/31 ,  H01L23/49866 ,  H01L23/50 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81447 ,  H01L2924/00014 ,  H01L2224/81455 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a Pad on Solder Mask (PoSM) semiconductor substrate package. For instance, in accordance with one embodiment, there is a substrate package having embodied therein a functional silicon die at a top layer of the substrate package; a solder resist layer beneath the functional silicon die of the substrate package; a plurality of die bumps at a bottom surface of the functional silicon die, the plurality of die bumps electrically interfacing the functional silicon die to a substrate through a plurality of solder balls at a top surface of the solder resist layer; each of the plurality of die bumps electrically interfaced to a nickel pad at least partially within the solder resist layer and beneath the solder balls; each of the plurality of die bumps electrically interfaced through the nickel pads to a conductive pad exposed at a bottom surface of the solder resist layer; and in which each of the conductive pads exposed at the bottom surface of the solder resist layer are electrically interfaced to an electrical trace at the substrate of the substrate package. Other related embodiments are disclosed.

公开(公告)号：US20230369232A1

公开(公告)日：2023-11-16

申请号：US17741988

申请日：2022-05-11

Applicant: Intel Corporation

Inventor： Hazwani Jaffar ,  Poh Boon Khoo ,  Hooi San Lam ,  Jiun Hann Sir ,  Eng Huat Goh

IPC: H01L23/538 ,  H01L25/18 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L23/5385 ,  H01L25/18 ,  H01L25/50 ,  H01L21/4853 ,  H01L25/105

Abstract: An electronic system includes a first substrate including first solder bumps on a bottom surface, the first solder bumps having a first solder bump surface opposite from the bottom surface; a processor integrated circuit (IC) die including at least one processor mounted on a top surface of the first substrate; and a companion component to the processor IC. The companion component includes a second substrate, second solder bumps, and third solder bumps. The second solder bumps include a second solder bump surface, and the third solder bumps include a third solder bump surface at a different height than the second solder bump surface. The second solder bump surface contacts the top surface of the first substrate and the third solder bump surface is at a same height as the first solder bump surface.

公开(公告)号：US11664317B2

公开(公告)日：2023-05-30

申请号：US17024263

申请日：2020-09-17

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Eng Huat Goh ,  MD Altaf Hossain

IPC: H01L23/538 ,  H01L23/522 ,  H01L23/31 ,  H01L23/50 ,  H01L23/498 ,  H01L25/065 ,  H01L49/02 ,  H01L21/56

CPC classification number: H01L23/5384 ,  H01L21/565 ,  H01L23/31 ,  H01L23/5223 ,  H01L23/5385 ,  H01L23/5386 ,  H01L28/40

Abstract: Disclosed embodiments include die-edge level passive devices for integrated-circuit device packages that provide a low-loss path to active and passive devices, by minimizing inductive loops.