公开(公告)号：US20230420379A1

公开(公告)日：2023-12-28

申请号：US17848059

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Seok Ling Lim ,  Hazwani Jaffar ,  Yean Ling Soon

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H01L23/66

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5385 ,  H01L23/552 ,  H01L23/66 ,  H01L21/4857 ,  H01L23/49822 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L24/08

Abstract: IC device package routing with metallization features comprising a pseudo-stripline architecture in which the stripline structure is provisioned, in part, by a routing structure separate from routing within the package substrate. A signal route within top metallization level of a package substrate may be electrically shielded, in part, with a metallization feature within a redistribution layer (RDL) of a routing structure that couples one or more IC chips to the package substrate. Accordingly, a package substrate may have fewer levels of metallization, reduced thickness, and/or lower cost while the IC device package still offers excellent EMI performance.

公开(公告)号：US20230369232A1

公开(公告)日：2023-11-16

申请号：US17741988

申请日：2022-05-11

Applicant: Intel Corporation

Inventor： Hazwani Jaffar ,  Poh Boon Khoo ,  Hooi San Lam ,  Jiun Hann Sir ,  Eng Huat Goh

IPC: H01L23/538 ,  H01L25/18 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L23/5385 ,  H01L25/18 ,  H01L25/50 ,  H01L21/4853 ,  H01L25/105

Abstract: An electronic system includes a first substrate including first solder bumps on a bottom surface, the first solder bumps having a first solder bump surface opposite from the bottom surface; a processor integrated circuit (IC) die including at least one processor mounted on a top surface of the first substrate; and a companion component to the processor IC. The companion component includes a second substrate, second solder bumps, and third solder bumps. The second solder bumps include a second solder bump surface, and the third solder bumps include a third solder bump surface at a different height than the second solder bump surface. The second solder bump surface contacts the top surface of the first substrate and the third solder bump surface is at a same height as the first solder bump surface.