Abstract:
A method, device, and system for traffic switching in Multi-Protocol Label Switching Traffic Engineering (MPLS TE) are disclosed. The method includes: transmitting traffic over a standby Label Switching Path (LSP) after detecting fault of an active LSP; detecting that the forwarding entry on the active LSP is delivered completely after the fault of the active LSP is rectified; and switching the traffic to the active LSP, and transmitting the traffic over the active LSP. The present invention ensures that the forwarding entry on the active LSP is delivered completely, and prevents packet loss and traffic loss in the case of switching the traffic back from the standby LSP to the active LSP, thus improving the user experience and enhancing the network availability and stability.
Abstract:
A data storage device and methods for storing and reading data are provided. The data storage device includes a data storage medium and second device. The data storage medium has an insulating layer, a first electrode layer over the insulating layer and at least one layer of resistance variable material over the first electrode layer. The second device includes a substrate and at least one conductive point configured to electrically contact the data storage medium.
Abstract:
A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, an insulative layer between the free and pinned layers, and a nonmagnetic filament contact in the insulative layer which electrically connects the free and pinned layers. The nonmagnetic filament contact is formed from a nonmagnetic source layer, also between the free and pinned layers. The filament contact directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.
Abstract:
A magnetic memory cell including a soft magnetic layer and a coupling layer, and methods of operating the memory cell are provided. The memory cell includes a stack with a free ferromagnetic layer and a pinned ferromagnetic layer, and a soft magnetic layer and a coupling layer may also be formed as layers in the stack. The coupling layer may cause antiferromagnetic coupling to induce the free ferromagnetic layer to be magnetized in a direction antiparallel to the magnetization of the soft magnetic layer, or the coupling layer may cause ferromagnetic coupling to induce the free ferromagnetic layer to be magnetized in a direction parallel to the magnetization of the soft magnetic layer. The coupling layer, through a coupling effect, reduces the critical switching current of the memory cell.
Abstract:
Systems and methods for diagnosing gas turbine engine faults are provided. In this regard, a representative method includes: dynamically assessing detected symptoms based, at least in part, on failure rates of components of the gas turbine engine as functions of usage of the components such that suspected faults are identified.
Abstract:
A method of forming a layer of material on a sidewall of a via with good thickness control. The method involves forming a layer of material with a conventional deposition process. The material formed on a field region surrounding the via is removed with a sputter etch process. Another layer of material is deposited thereon, wherein the sputter etch-deposition cycle is repeated as necessary to achieve a desired sidewall thickness. With this method, the thickness of the material deposited on the sidewall is linearly dependent on the number of process cycles, thus providing good thickness control. The method may be used to form a resistance variable material, e.g., a phase-change material, on a via sidewall for use in a memory element.
Abstract:
A programmable resistance memory element and method of forming the same. The memory element includes a first electrode, a dielectric layer over the first electrode and a second electrode over the dielectric layer. The dielectric layer and the second electrode each have sidewalls. A layer of programmable resistance material, e.g., a phase change material, is in contact with the first electrode and at least a portion of the sidewalls of the dielectric layer and the second electrode. Memory devices including memory elements and systems incorporating such memory devices are also disclosed.
Abstract:
The present application concerns concentrated protein formulations with reduced viscosity, which are particularly suitable for subcutaneous administration. The application further concerns a method for reducing the viscosity of concentrated protein formulations.
Abstract:
An improved memory array architecture and cell design is disclosed in which the cell employs two access transistors. In one embodiment, the two access transistors in each cell are coupled at one of their channel terminals to a memory element, which in turn is connected to a bit line. The other of the channel terminals are effectively tied together via reference lines. The word lines (i.e., gates) of the two access transistors are also tied together. The result in a preferred embodiment is a cell having two access transistors wired and accessed in parallel. With such a configuration, the widths of the access transistors can be made one-half the width of more-traditional one-access-transistor designs, saving layout space in that (first) dimension. Moreover, because the word lines of adjacent cells will be deselected, the improved design does not require cell-to-cell isolation (e.g., trench isolation) in the other (second) dimension. The result, when applied to a phase change memory, comprises about a 37% reduction in layout area from previous cell designs.
Abstract:
The present disclosure includes methods, devices, modules, and systems for sensing memory cells using a state machine. One method embodiment includes generating a first sensing reference according to a first output of a state machine. The method includes bifurcating a range of possible programmed levels to which a memory cell can be programmed with the first sensing reference. The method also includes generating a second sensing reference according to a second output of the state machine. The method further includes determining a programmed level of the memory cell with the second generated sensing reference.