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公开(公告)号:US20250120298A1
公开(公告)日:2025-04-10
申请号:US18985350
申请日:2024-12-18
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Wei YANG , Guangcai Yuan , Ce Ning , Xinhong Lu , Tianmin Zhou , Xin Yang
IPC: H10K59/121 , H10D86/40 , H10D86/60 , H10K59/12 , H10K59/123 , H10K59/131
Abstract: The present disclosure relates to an OLED display panel and display device. The OLED display panel includes: a display area, a bending area and a bonding area, the display panel further includes: a base substrate; a first semiconductor pattern on the base substrate; a first insulating layer group on the first semiconductor pattern; a second semiconductor pattern on the first insulating layer group; a second insulating layer group on the second semiconductor pattern; first via holes in the first insulating layer group and the second insulating layer group; second via holes in the second insulating layer group, the display panel further includes: a metal trace, located on a side of the second insulating layer group away from the base substrate, and configured to connect a trace in the display area to a circuit board of the bending area; and a second source electrode and/or a second drain electrode.
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公开(公告)号:US12217651B2
公开(公告)日:2025-02-04
申请号:US17913258
申请日:2021-11-04
Applicant: BOE Technology Group Co., Ltd.
Inventor: Lizhong Wang , Ce Ning , Yunping Di , Binbin Tong , Chengfu Xu , Dapeng Xue , Shuilang Dong , Nianqi Yao
IPC: G09G3/20
Abstract: A display substrate, a manufacturing method thereof and a display apparatus are provided. In the present disclosure, a first transistor group with oxide semiconductor as an active layer material is disposed on a side of a second transistor group with polysilicon as an active layer material away from the base, and an area enclosed by orthographic projections of the transistors in the first transistor group on the base is overlapped with an area enclosed by orthographic projections of the transistors in the second transistor group on the base. Stable performance of the transistors included can be ensured in a manufacturing process of the first transistor group and the second transistor group located in different layers, and at the same time, an area occupied by the driving circuit can be reduced so as to decrease a frame width of a display apparatus or improve resolution of the display apparatus.
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公开(公告)号:US20240261785A1
公开(公告)日:2024-08-08
申请号:US18018795
申请日:2021-12-31
Applicant: BOE Technology Group Co., Ltd.
Inventor: Feifei Li , Bolin Fan , Ce Ning , Zhengliang Li , Hehe Hu , Nianqi Yao , Jiayu He , Jie Huang , Kun Zhao
IPC: B01L3/00
CPC classification number: B01L3/502761 , B01L2200/0647 , B01L2200/12 , B01L2300/0645 , B01L2300/0848 , B01L2400/0415
Abstract: Provided is a micro-nano fluidic substrate, a chip, a preparation method, and a system. The micro-nano fluidic substrate includes: a base; an electrode layer located on the base, the electrode layer includes a first electrode, a second electrode, and a control electrode; and a film layer located on the electrode layer and far away from the base, the film layer includes a groove layer, a nano-channel and a micro-channel, the groove layer includes a first groove, the nano-channel is located in the first groove, an orthographic projection of the nano-channel on the base at least partially coincides with an orthographic projection of the control electrode on the base, and the micro-channel is in communication with the nano-channel, the micro-channel includes a first micro-channel and a second micro-channel, and the first micro-channel is in communication with the first electrode, the second micro-channel is in communication with the second electrode.
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84.
公开(公告)号:US20240243206A1
公开(公告)日:2024-07-18
申请号:US18686604
申请日:2021-08-27
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Guangcai Yuan , Lingyan Liang , Hongtao Cao , Fengjuan Liu , Ce Ning , Fei Wang , Hehe Hu , Xiaolong Wang
IPC: H01L29/786 , H01L27/12 , H01L29/04 , H01L29/66
CPC classification number: H01L29/7869 , H01L27/1222 , H01L29/04 , H01L29/66742
Abstract: A thin film transistor; includes a substrate; and a semiconductor layer provided on the substrate. The semiconductor layer includes a first surface proximate to the substrate and a second surface away from the substrate, and the semiconductor layer is made of a metal oxide semiconductor material. The semiconductor layer has a channel region; and crystals of metal oxide semiconductor are formed at least in the channel region of the semiconductor layer and proximate to the first surface or the second surface.
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公开(公告)号:US20240194698A1
公开(公告)日:2024-06-13
申请号:US17772395
申请日:2021-06-29
Applicant: BOE Technology Group Co., Ltd.
Inventor: Lizhong Wang , Ce Ning , Yunping Di , Binbin Tong , Zhen Zhang , Zhenyu Zhang , Fuqiang Li , Chengfu Xu
IPC: H01L27/12
CPC classification number: H01L27/1251 , H01L27/1222 , H01L27/124 , H01L27/127
Abstract: A displaying base plate and a manufacturing method thereof, and a displaying device. The displaying base plate includes an active area and a non-active area located at the periphery of the active area, wherein the active area includes an opening area and a non-opening area. The displaying base plate includes a substrate and a thin-film transistor disposed on one side of the substrate, wherein the thin-film transistor includes a grid electrode, an active layer, a source-drain electrode and an auxiliary film layer, an excavation area is disposed on the auxiliary film layer, and an orthographic projection of the excavation area on the substrate at least partially covers the opening area.
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86.
公开(公告)号:US20240186379A1
公开(公告)日:2024-06-06
申请号:US17798347
申请日:2021-10-22
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Hehe Hu , Fengjuan Liu , Guangcai Yuan , Jiayu He , Ce Ning , Zhengliang Li , Kun Zhao
IPC: H01L29/10 , H01L21/385 , H01L29/24 , H01L29/66 , H01L29/786
CPC classification number: H01L29/1041 , H01L21/385 , H01L29/24 , H01L29/66969 , H01L29/7869
Abstract: Provided is a method for manufacturing a metal-oxide thin-film transistor (TFT). The method includes: forming, on a base substrate, an active layer including a metal oxide semiconductor, and a functional layer laminated on the active layer and containing a lanthanide element; and annealing the active layer and the functional layer, such that the lanthanide element in the functional layer is diffused into the active layer.
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87.
公开(公告)号:US11631362B2
公开(公告)日:2023-04-18
申请号:US17535127
申请日:2021-11-24
Applicant: BOE Technology Group Co., Ltd.
Inventor: Shuilang Dong , Shanshan Xu , Guangcai Yuan , Zhanfeng Cao , Ce Ning , Lizhong Wang , Dapeng Xue , Nianqi Yao
IPC: G09G3/3266 , G09G3/20 , G11C19/28
Abstract: A shift register unit includes an input sub-circuit, a pull-down node driving sub-circuit and an output sub-circuit. The pull-down node driving sub-circuit includes a first connection unit, a first voltage-reduction unit and a second connection unit, and configured to: under the control of the first voltage signal terminal and the pull-up node, transmit a first voltage signal from the first voltage signal terminal to the first pull-down node via the first connection unit, and reduce a voltage applied to the second connection unit via the first voltage-reduction unit; and transmit a second voltage signal from the second voltage signal terminal to the first pull-down node via the second connection unit under the control of the pull-up node.
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公开(公告)号:US20230006070A1
公开(公告)日:2023-01-05
申请号:US17782035
申请日:2021-05-27
Applicant: BOE Technology Group Co., Ltd.
Inventor: Jie Huang , Ce Ning , Zhengliang Li , Hehe Hu , Jiayu He , Nianqi Yao , Kun Zhao , Feng Qu , Xiaochun Xu
IPC: H01L29/786 , H01L29/66 , H01L27/12
Abstract: A semiconductor substrate manufacturing method and a semiconductor substrate. The manufacturing method includes: forming a first semiconductor layer on the base substrate at a first temperature with a first oxide semiconductor material; forming the second semiconductor layer directly on the first semiconductor layer with a second oxide semiconductor material; and performing a patterning process such that the first semiconductor layer and the second semiconductor layer are respectively patterned into a seed layer and a first channel layer. Both the first oxide semiconductor material and the second oxide semiconductor material are capable of forming crystalline phases at a second temperature, the second temperature is less than or equal to 40° C., and the first temperature is greater than or equal to 100° C.
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公开(公告)号:US11532686B2
公开(公告)日:2022-12-20
申请号:US16330719
申请日:2018-09-11
Applicant: BOE Technology Group Co., Ltd.
Inventor: Xinhong Lu , Ke Wang , Hehe Hu , Ce Ning , Wei Yang
IPC: H01L29/78 , H01L27/32 , H01L29/786
Abstract: An array substrate includes a base substrate; a first thin film transistor on the base substrate and including a first active layer, a first gate electrode, a first source electrode and a first drain electrode; a second thin film transistor on the base substrate and including a second active layer, a second gate electrode, a second source electrode and a second drain electrode; a first gate insulating layer between the first active layer and the first gate electrode; and a second gate insulating layer between the second active layer and the second gate electrode, the second gate insulating layer being different from the first gate insulating layer. The first source electrode, the first drain electrode, and the second gate electrode are in a same layer. The first source electrode and the first drain electrode are on a side of the second gate insulating layer distal to the base substrate.
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公开(公告)号:US20220344517A1
公开(公告)日:2022-10-27
申请号:US17763297
申请日:2021-04-30
Applicant: BOE Technology Group Co., Ltd.
Inventor: Jie Huang , Zhengliang Li , Ce Ning , Hehe Hu , Nianqi Yao , Kun Zhao , Fengjuan Liu , Tianmin Zhou , Liping Lei
IPC: H01L29/786
Abstract: A thin film transistor includes a gate electrode, an active layer, a gate insulating layer located between the gate electrode and the active layer, and a source electrode and a drain electrode electrically connected to the active layer. The active layer includes a channel layer and at least one channel protection layer; a material of each of the channel layer and the at least one channel protection layer is a metal oxide semiconductor material. The at least one channel protection layer is a crystallizing layer, and metal elements of the at least one channel protection layer include non-rare earth metal elements including In, Ga, Zn and Sn.
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