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    APPARATUS AND METHOD FOR EXTENDED NITRIDE LAYER IN A FLASH MEMORY
    82.
    发明申请
    APPARATUS AND METHOD FOR EXTENDED NITRIDE LAYER IN A FLASH MEMORY 有权
    闪存中扩展的氮化层的装置和方法

    公开(公告)号：US20110199819A1

    公开(公告)日：2011-08-18

    申请号：US12706710

    申请日：2010-02-16

    Applicant: Shenqing Fang ,  Youseok Suh

    Inventor： Shenqing Fang ,  Youseok Suh

    IPC: G11C16/04 ,  H01L29/792

    CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/66833

    Abstract: A method and apparatus for storing information is provided. A core region of memory includes a semiconductor layer, at least one shallow trench, an insulator, and a charge-trapping layer. The semiconductor layer includes at least one source/drain region, and the insulator disposed above the source/drain region. The charge trapping layer is within the insulator, and the charge trapping layer is above the entire width of the source/drain region, and extends at least one angstrom beyond the width of the source/drain region, so that a portion the charge trapping layer extends into at least one shallow trench.

    Abstract translation: 提供了一种用于存储信息的方法和装置。 存储器的核心区域包括半导体层，至少一个浅沟槽，绝缘体和电荷俘获层。 半导体层包括至少一个源极/漏极区域，以及设置在源极/漏极区域上方的绝缘体。 电荷捕获层在绝缘体内，并且电荷捕获层高于源/漏区的整个宽度，并且延伸超过源极/漏极区的宽度至少一埃，使得电荷捕获层 延伸到至少一个浅沟槽中。

    Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductur applications
    83.
    发明授权
    Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductur applications 有权
    通过使用非保形膜的自对准图案化方法，并回扫闪存和其他半导体应用

    公开(公告)号：US07943980B2

    公开(公告)日：2011-05-17

    申请号：US12891532

    申请日：2010-09-27

    Applicant: Shenqing Fang ,  Kuo-Tung Chang ,  Tim Thurgate ,  YouSeok Suh ,  Allison Holbrook

    Inventor： Shenqing Fang ,  Kuo-Tung Chang ,  Tim Thurgate ,  YouSeok Suh ,  Allison Holbrook

    IPC: H01L29/76

    CPC classification number: H01L27/11568 ,  H01L27/115

    Abstract: A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.

    Abstract translation: 公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于结垢。 在本发明中，在电荷捕获层上沉积非保形氧化物，以在芯源极/漏极区域的顶部上形成厚的氧化物，并在STI沟槽的顶部形成空隙。 对STI氧化物上的捕获层上的夹断氧化物和薄氧化物进行蚀刻。 然后在核心单元之间部分蚀刻捕获层。 进行捕获层上的氧化物的偏移。 并形成顶部氧化物。 顶部氧化物将剩余的陷阱层转化为氧化物，从而隔离陷阱层。

    NAND MEMORY CELL STRING HAVING A STACKED SELECT GATE STRUCTURE AND PROCESS FOR FOR FORMING SAME
    85.
    发明申请
    NAND MEMORY CELL STRING HAVING A STACKED SELECT GATE STRUCTURE AND PROCESS FOR FOR FORMING SAME 审中-公开
    具有堆叠的选择门结构的NAND存储器单元和用于形成其的处理

    公开(公告)号：US20100322006A1

    公开(公告)日：2010-12-23

    申请号：US12489226

    申请日：2009-06-22

    Applicant: Ming Sang Kwan ,  Shenqing Fang ,  Youseok Suh ,  Michael Van Buskirk

    Inventor： Ming Sang Kwan ,  Shenqing Fang ,  Youseok Suh ,  Michael Van Buskirk

    IPC: G11C16/04 ,  H01S4/00

    CPC classification number: G11C16/16 ,  G11C16/0483 ,  Y10T29/49002

    Abstract: A memory cell string is disclosed. The memory cell string includes a first select gate that includes a first plurality of elements. A plurality of wordlines are coupled to the first select gate and a second select gate, that includes a second plurality of elements, is coupled to the plurality of wordlines. The distances between one element of the first and the second plurality of elements and the plurality of wordlines are the same as the distances that exist between each wordline of the plurality of wordlines.

    Abstract translation: 公开了一种存储单元串。 存储单元串包括包括第一多个元件的第一选择栅极。 多个字线耦合到第一选择栅极，并且包括第二多个元件的第二选择栅极耦合到多个字线。 第一和第二多个元件的一个元件与多个字线之间的距离与存在于多个字线的每个字线之间的距离相同。

    SCALED DOWN SELECT GATES OF NAND FLASH MEMORY CELL STRINGS AND METHOD OF FORMING SAME
    86.
    发明申请
    SCALED DOWN SELECT GATES OF NAND FLASH MEMORY CELL STRINGS AND METHOD OF FORMING SAME 有权
    NAND FLASH MEMORY CELL STRING的缩放选择门及其形成方法

    公开(公告)号：US20100085811A1

    公开(公告)日：2010-04-08

    申请号：US12246981

    申请日：2008-10-07

    Applicant: YouSeok SUH ,  Shenqing FANG ,  Kuo-Tung CHANG

    Inventor： YouSeok SUH ,  Shenqing FANG ,  Kuo-Tung CHANG

    IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/115 ,  G11C16/0483

    Abstract: A NAND flash memory cell string having scaled down select gates. The NAND flash memory cell string includes a first select gate that has a width of 140 nm or less and a plurality of wordlines that are coupled to the first select gate. Gates associated with the plurality of wordlines are formed of p+ polysilicon. A second select gate that has a width of 140 nm or less is coupled to the plurality of wordlines.

    Abstract translation: 具有按比例缩小的选择门的NAND快闪存储器单元串。 NAND闪存单元串包括具有140nm或更小的宽度的第一选择栅极和耦合到第一选择栅极的多个字线。 与多个字线相关联的门由p +多晶硅形成。 具有140nm或更小的宽度的第二选择栅极耦合到多个字线。

    MEMORY DEVICE PERIPHERAL INTERCONNECTS AND METHOD OF MANUFACTURING
    87.
    发明申请
    MEMORY DEVICE PERIPHERAL INTERCONNECTS AND METHOD OF MANUFACTURING 有权
    存储器件外围互连和制造方法

    公开(公告)号：US20090289369A1

    公开(公告)日：2009-11-26

    申请号：US12512960

    申请日：2009-07-30

    Applicant: Shenqing FANG ,  Wenmei LI

    Inventor： Shenqing FANG ,  Wenmei LI

    IPC: H01L23/522 ,  H01L21/768

    CPC classification number: H01L23/522 ,  H01L21/76816 ,  H01L23/485 ,  H01L27/1052 ,  H01L27/11529 ,  H01L27/11531 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit memory device, in one embodiment, includes a substrate and first and second inter-level dielectric layers successively disposed on the substrate. One or more contacts in the peripheral extend through the first inter-level dielectric layer to respective components. One or more vias and a plurality of dummy vias extend through the second inter-level dielectric layer in the peripheral area. Each of the one or more peripheral vias extend to a respective peripheral contact. The peripheral dummy vias are located proximate the peripheral vias.

    Abstract translation: 在一个实施例中，集成电路存储器件包括衬底和连续地设置在衬底上的第一和第二级间介电层。 外围设备中的一个或多个触点延伸穿过第一层间电介质层到相应的部件。 一个或多个通孔和多个虚拟通孔延伸穿过周边区域中的第二层间电介质层。 一个或多个外围通孔中的每一个延伸到相应的外围触点。 外围的虚拟通孔位于外围通孔附近。

    Flash memory cell with a flair gate
    89.
    发明申请
    Flash memory cell with a flair gate 有权
    闪存单元，带有风格门

    公开(公告)号：US20080277712A1

    公开(公告)日：2008-11-13

    申请号：US11801823

    申请日：2007-05-10

    Applicant: Meng Ding ,  YouSeok Suh ,  Shenqing Fang ,  Kuo-Tung Chang

    Inventor： Meng Ding ,  YouSeok Suh ,  Shenqing Fang ,  Kuo-Tung Chang

    IPC: H01L29/788 ,  H01L21/3205 ,  H01L21/76

    CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/762 ,  H01L21/76224 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/792

    Abstract: An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width.

    Abstract translation: 本发明的实施例涉及一种形成存储单元的方法。 该方法包括蚀刻衬底中的沟槽并用氧化物填充沟槽以形成浅沟槽隔离（STI）区域。 与STI区域接触的衬底的有源区域的一部分形成位线STI边缘。 该方法还包括在衬底的有源区上方和STI区上形成栅极结构。 栅极结构具有基本上在衬底的有源区域的中心上方的第一宽度和基本上位于STI边缘的第二宽度，并且第二宽度大于第一宽度。

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