公开(公告)号：US08455268B2

公开(公告)日：2013-06-04

申请号：US11848515

申请日：2007-08-31

Applicant: Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Rinji Sugino ,  Chi Chang ,  Huaqiang Wu

Inventor： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Rinji Sugino ,  Chi Chang ,  Huaqiang Wu

IPC: H01L21/00 ,  H01L21/311

CPC classification number: H01L29/7923 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

Abstract: Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.

Abstract translation: 提供了替换/重整存储单元的电荷存储元件周围的顶部氧化物的方法和提高存储单元的电荷存储元件周围的顶部氧化物的质量的方法。 该方法可以包括从存储器单元去除第一顶部氧化物上的第一多晶硅; 从存储器单元中去除第一顶部氧化物; 以及在所述电荷存储元件周围形成第二顶部氧化物。 可以通过氧化电荷存储元件的一部分或通过在电荷存储元件上形成牺牲层并将牺牲层氧化成第二顶部氧化物来形成第二顶部氧化物。

公开(公告)号：US20110272775A1

公开(公告)日：2011-11-10

申请号：US13183373

申请日：2011-07-14

Applicant: Eunha KIM ,  Jeremy WAHL ,  Shenqing FANG ,  YouSeok SUH ,  Kuo-Tung CHANG ,  Yi MA ,  Rinji SUGINO ,  Jean YANG

Inventor： Eunha KIM ,  Jeremy WAHL ,  Shenqing FANG ,  YouSeok SUH ,  Kuo-Tung CHANG ,  Yi MA ,  Rinji SUGINO ,  Jean YANG

IPC: H01L29/02

CPC classification number: H01L21/02675 ,  H01L21/02592 ,  H01L21/02691

Abstract: A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.

Abstract translation: 提出了半导体制造系统和方法。 三维多层集成电路制造方法可以包括通过利用受控激光层形成退火工艺形成第一器件层并在第一器件层顶部形成第二器件层，并以最小的有害热传递到第一层。 可以利用受控激光结晶过程，并且受控激光器可以包括产生非晶层; 限定非晶层中的结晶区域，其中结晶区域被限定为促进单晶生长（即防止多晶生长）; 以及将激光施加到结晶区域，其中以防止不希望的热传递到另一层的方式施加激光。

公开(公告)号：US20100065940A1

公开(公告)日：2010-03-18

申请号：US12209478

申请日：2008-09-12

Applicant: Eunha KIM ,  Jeremy WAHL ,  Shenqing FANG ,  YouSeok SUH ,  Kuo-Tung CHANG ,  Yi MA ,  Rinji SUGINO ,  Jean YANG

Inventor： Eunha KIM ,  Jeremy WAHL ,  Shenqing FANG ,  YouSeok SUH ,  Kuo-Tung CHANG ,  Yi MA ,  Rinji SUGINO ,  Jean YANG

IPC: H01L29/00 ,  H01L21/00

CPC classification number: H01L21/02675 ,  H01L21/02592 ,  H01L21/02691

Abstract: A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.

Abstract translation: 提出了半导体制造系统和方法。 三维多层集成电路制造方法可以包括通过利用受控激光层形成退火工艺形成第一器件层并在第一器件层顶部形成第二器件层，并以最小的有害热传递到第一层。 可以利用受控激光结晶过程，并且受控激光器可以包括产生非晶层; 限定非晶层中的结晶区域，其中结晶区域被限定为促进单晶生长（即防止多晶生长）; 以及将激光施加到结晶区域，其中以防止不希望的热传递到另一层的方式施加激光。

公开(公告)号：US20090269916A1

公开(公告)日：2009-10-29

申请号：US12110974

申请日：2008-04-28

Applicant: Inkuk KANG ,  Gang XUE ,  Shenqing FANG ,  Rinji SUGINO ,  Yi MA

Inventor： Inkuk KANG ,  Gang XUE ,  Shenqing FANG ,  Rinji SUGINO ,  Yi MA

IPC: H01L21/28 ,  H01L21/306

CPC classification number: H01L27/11568 ,  H01L29/66795 ,  H01L29/7854

Abstract: Methods for fabricating a FIN structure with a semicircular top surface and rounded top surface corners and edges are disclosed. As a part of a disclosed method, a FIN structure is formed in a semiconductor substrate. The FIN structure includes a top surface having corners and edges. The FIN structure is annealed where the annealing causes the top surface to have a semicircular shape and the top surface corners and edges to be rounded.

Abstract translation: 公开了制造具有半圆顶表面和圆顶顶表面拐角和边缘的FIN结构的方法。 作为所公开的方法的一部分，在半导体衬底中形成FIN结构。 FIN结构包括具有拐角和边缘的顶表面。 FIN结构退火，其中退火导致顶表面具有半圆形形状，并且顶表面拐角和边缘被倒圆。

公开(公告)号：US20080142874A1

公开(公告)日：2008-06-19

申请号：US11611860

申请日：2006-12-16

Applicant: Shenqing Fang ,  Rinji Sugino ,  Jayendra Bhakta ,  Takashi Orimoto ,  Hiroyuki Nansei ,  Yukio Hayakawa ,  Hidehiko Shiraiwa ,  Takayuki Maruyama ,  Kuo-Tung Chang ,  YouSeok Suh ,  Amol Ramesh Joshi ,  Harpreet Sachar ,  Simon Siu-Sing Chan

Inventor： Shenqing Fang ,  Rinji Sugino ,  Jayendra Bhakta ,  Takashi Orimoto ,  Hiroyuki Nansei ,  Yukio Hayakawa ,  Hidehiko Shiraiwa ,  Takayuki Maruyama ,  Kuo-Tung Chang ,  YouSeok Suh ,  Amol Ramesh Joshi ,  Harpreet Sachar ,  Simon Siu-Sing Chan

IPC: H01L29/792 ,  H01L21/3205

CPC classification number: H01L29/792 ,  H01L29/66833

Abstract: A method for forming an integrated circuit system is provided including forming a substrate; forming a stack over the substrate, the stack having a sidewall and formed from a charge trap layer and a semi-conducting layer; and slot plane antenna oxidizing the stack for forming a protection enclosure having a protection layer along the sidewall.

Abstract translation: 提供一种用于形成集成电路系统的方法，包括：形成衬底; 在衬底上形成堆叠，所述堆叠具有侧壁并由电荷陷阱层和半导体层形成; 以及缝隙平面天线，用于氧化该叠层以形成具有沿该侧壁的保护层的保护罩。

公开(公告)号：US20080135913A1

公开(公告)日：2008-06-12

申请号：US11608032

申请日：2006-12-07

Applicant: Rinji Sugino ,  Timothy Thurgate ,  Jean Yee-Mei Yang ,  Michael Brennan

Inventor： Rinji Sugino ,  Timothy Thurgate ,  Jean Yee-Mei Yang ,  Michael Brennan

IPC: H01L29/788

CPC classification number: H01L29/792 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

Abstract: A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells.

Abstract translation: 存储器件包括形成在衬底上的一组存储器单元，每个存储器单元包括形成在衬底中的源极区域和漏极区域。 存储器件还包括形成在源极区域和漏极区域的顶表面上以及在该组存储器单元的侧表面上的保护层。

公开(公告)号：US06884681B1

公开(公告)日：2005-04-26

申请号：US10672093

申请日：2003-09-26

Applicant: Tazrien Kamal ,  Arvind Halliyal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Rinji Sugino

Inventor： Tazrien Kamal ,  Arvind Halliyal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Rinji Sugino

IPC: H01L21/336 ,  H01L21/8246

CPC classification number: H01L27/11568 ,  H01L29/66833

Abstract: A method for manufacturing a MirrorBit® Flash memory includes providing a semiconductor substrate and successively depositing a first insulating layer, a charge-trapping layer, and a second insulating layer. First and second bitlines are implanted and wordlines are formed before completing the memory. Spacers are formed between the wordlines and an inter-layer dielectric layer is formed over the wordlines. One or more of the second insulating layer, wordlines, spacers, and inter-layer dielectric layers are deuterated, replacing hydrogen bonds with deuterium, thus improving data retention and substantially reducing charge loss.

Abstract translation: 一种用于制造MirrorBit（闪存）闪存的方法包括：提供半导体衬底，并依次沉积第一绝缘层，电荷俘获层和第二绝缘层。 植入第一和第二位线，并在完成内存之前形成字线。 在字线之间形成间隔，并且在字线之间形成层间电介质层。 第二绝缘层，字线，间隔层和层间电介质层中的一个或多个被氘化，用氘替代氢键，从而改善数据保留并显着降低电荷损失。

公开(公告)号：US08987092B2

公开(公告)日：2015-03-24

申请号：US12110974

申请日：2008-04-28

Applicant: Inkuk Kang ,  Gang Xue ,  Shenqing Fang ,  Rinji Sugino ,  Yi Ma

Inventor： Inkuk Kang ,  Gang Xue ,  Shenqing Fang ,  Rinji Sugino ,  Yi Ma

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/11568 ,  H01L29/66795 ,  H01L29/7854

Abstract: Methods for fabricating a FIN structure with a semicircular top surface and rounded top surface corners and edges are disclosed. As a part of a disclosed method, a FIN structure is formed in a semiconductor substrate. The FIN structure includes a top surface having corners and edges. The FIN structure is annealed where the annealing causes the top surface to have a semicircular shape and the top surface corners and edges to be rounded.

Abstract translation: 公开了制造具有半圆顶表面和圆顶顶表面拐角和边缘的FIN结构的方法。 作为所公开的方法的一部分，在半导体衬底中形成FIN结构。 FIN结构包括具有拐角和边缘的顶表面。 FIN结构退火，其中退火导致顶表面具有半圆形形状，并且顶表面拐角和边缘被倒圆。

公开(公告)号：US20080061359A1

公开(公告)日：2008-03-13

申请号：US11702847

申请日：2007-02-05

Applicant: Chungho Lee ,  Hiroyuki Kinoshita ,  Zoran Krivokapic ,  Wei Zheng ,  Mark Chang ,  Rinji Sugino ,  Chi Chang

Inventor： Chungho Lee ,  Hiroyuki Kinoshita ,  Zoran Krivokapic ,  Wei Zheng ,  Mark Chang ,  Rinji Sugino ,  Chi Chang

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L27/11568 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7885 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

Abstract: An embodiment of the present invention is directed to a memory cell. The memory cell includes a stack formed over a substrate. The stack includes a gate oxide layer and an overlying polycrystalline silicon layer. The stack further includes first and second undercut regions formed under the polycrystalline silicon layer and adjacent to the gate oxide layer. The memory cell further includes a first charge storage element formed in the first undercut region and a second charge storage element formed in the second undercut region.

Abstract translation: 本发明的实施例涉及存储单元。 存储单元包括形成在衬底上的堆叠。 堆叠包括栅极氧化物层和上覆的多晶硅层。 堆叠还包括形成在多晶硅层下方并与栅极氧化物层相邻的第一和第二底切区域。 存储单元还包括形成在第一底切区域中的第一电荷存储元件和形成在第二底切区域中的第二电荷存储元件。

公开(公告)号：US07163860B1

公开(公告)日：2007-01-16

申请号：US10430471

申请日：2003-05-06

Applicant: Tazrien Kamal ,  Yun Wu ,  Mark Ramsbey ,  Jean Yee-Mei Yang ,  Arvind Halliyal ,  Rinji Sugino ,  Hidehiko Shiraiwa ,  Fred T K Cheung

Inventor： Tazrien Kamal ,  Yun Wu ,  Mark Ramsbey ,  Jean Yee-Mei Yang ,  Arvind Halliyal ,  Rinji Sugino ,  Hidehiko Shiraiwa ,  Fred T K Cheung

IPC: H01L21/8247

CPC classification number: H01L21/28282 ,  H01L29/7923 ,  Y10S438/954

Abstract: The present invention, in one embodiment, relates to a process for fabricating a charge trapping dielectric flash memory device including steps of providing a semiconductor substrate having formed thereon a gate stack comprising a charge trapping dielectric charge storage layer and a control gate electrode overlying the charge trapping dielectric charge storage layer; forming an oxide layer over at least the gate stack; and depositing a spacer layer over the gate stack, wherein the depositing step deposits a spacer material having a reduced hydrogen content relative to a hydrogen content of a conventional spacer material.

Abstract translation: 本发明在一个实施例中涉及一种用于制造电荷俘获电介质闪存器件的方法，该器件包括提供半导体衬底，该半导体衬底上形成有包括电荷俘获介电电荷存储层和覆盖电荷的控制栅电极 俘获介电电荷存储层; 至少在所述栅叠层上形成氧化层; 以及在所述栅极堆叠上沉积间隔层，其中所述沉积步骤沉积相对于常规间隔物材料的氢含量具有降低的氢含量的间隔物材料。