Invention Application
US20100085811A1 SCALED DOWN SELECT GATES OF NAND FLASH MEMORY CELL STRINGS AND METHOD OF FORMING SAME
有权
NAND FLASH MEMORY CELL STRING的缩放选择门及其形成方法
- Patent Title: SCALED DOWN SELECT GATES OF NAND FLASH MEMORY CELL STRINGS AND METHOD OF FORMING SAME
- Patent Title (中): NAND FLASH MEMORY CELL STRING的缩放选择门及其形成方法
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Application No.: US12246981Application Date: 2008-10-07
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Publication No.: US20100085811A1Publication Date: 2010-04-08
- Inventor: YouSeok SUH , Shenqing FANG , Kuo-Tung CHANG
- Applicant: YouSeok SUH , Shenqing FANG , Kuo-Tung CHANG
- Main IPC: G11C16/04
- IPC: G11C16/04 ; H01L21/8247 ; H01L27/115
Abstract:
A NAND flash memory cell string having scaled down select gates. The NAND flash memory cell string includes a first select gate that has a width of 140 nm or less and a plurality of wordlines that are coupled to the first select gate. Gates associated with the plurality of wordlines are formed of p+ polysilicon. A second select gate that has a width of 140 nm or less is coupled to the plurality of wordlines.
Public/Granted literature
- US07907448B2 Scaled down select gates of NAND flash memory cell strings and method of forming same Public/Granted day:2011-03-15
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