公开(公告)号：US20120268981A1

公开(公告)日：2012-10-25

申请号：US13456195

申请日：2012-04-25

Applicant: SATORU HANZAWA ,  Fumihiko Nitta ,  Nozomu Matsuzaki ,  Toshihiro Tanaka

Inventor： SATORU HANZAWA ,  Fumihiko Nitta ,  Nozomu Matsuzaki ,  Toshihiro Tanaka

IPC: G11C11/21

CPC classification number: G11C5/06 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144

Abstract: In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.

Abstract translation: 在包括由可变电阻器使用存储元件的存储器单元和选择晶体管形成的存储单元阵列的半导体器件中，缓冲单元布置在读出放大器和存储单元阵列之间以及字驱动器和存储单元阵列之间 。 存储单元中的电阻存储元件通过形成在电阻存储元件上方的触点连接到位线。 同时，在缓冲单元中，电阻性存储元件之上不形成接触，并且在处理存储单元中的接触时保持被绝缘体覆盖的状态。 通过这种处理方法，可以避免在电阻存储元件中使用的硫族化物膜的曝光和升华。

公开(公告)号：US08232543B2

公开(公告)日：2012-07-31

申请号：US12987606

申请日：2011-01-10

Applicant: Masahiro Moniwa ,  Nozomu Matsuzaki ,  Riichiro Takemura

Inventor： Masahiro Moniwa ,  Nozomu Matsuzaki ,  Riichiro Takemura

IPC: H01L31/032 ,  H01L45/00

CPC classification number: H01L45/144 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

Abstract: A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element.Between MISFET of the region which forms one memory cell, and MISFET which adjoined it, each source of MISFET adjoins in the front surface of a semiconductor substrate, insulating. And the multi-layer structure of a phase change film, and the electric conduction film of specific resistance lower than the specific resistance is formed in the plan view of the front surface of a semiconductor substrate ranging over each source of both MISFET, and a plug and a plug stacked on it. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of a semiconductor substrate, and an electric conduction film sends the current of a parallel direction on the surface of a semiconductor substrate.

Abstract translation: 实现了容易形成相变膜的半导体器件及其制造方法，在使用相变膜作为存储元件时实现高集成度。 在形成一个存储单元的区域的MISFET和与其相邻的MISFET之间，MISFET的每个源极邻接在半导体衬底的前表面中，绝缘。 并且在两个MISFET的每个源上的半导体衬底的前表面的平面图中形成相变膜的多层结构和比电阻率低的电阻率的导电膜，并且插塞 和堆叠在其上的插头。 多层结构用作在半导体衬底的表面上平行延伸并存在的布线，并且导电膜在半导体衬底的表面上发送平行方向的电流。

公开(公告)号：US08179739B2

公开(公告)日：2012-05-15

申请号：US12672685

申请日：2007-08-10

Applicant: Satoru Hanzawa ,  Fumihiko Nitta ,  Nozomu Matsuzaki ,  Toshihiro Tanaka

Inventor： Satoru Hanzawa ,  Fumihiko Nitta ,  Nozomu Matsuzaki ,  Toshihiro Tanaka

IPC: G11C8/00

CPC classification number: G11C5/06 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144

Abstract: A technique capable of manufacturing a semiconductor device without posing contamination in a manufacturing apparatus regarding a phase change memory including a memory cell array formed of memory cells using a storage element (RE) by a variable resistor and a select transistor (CT). A buffer cell is arranged between a sense amplifier (SA) and a memory cell array (MCA) and between a word driver (WDB) and the memory cell array. The buffer cell is formed of the resistive storage element (RE) and the select transistor (CT) same as those of the memory cell. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.

Abstract translation: 一种能够制造半导体器件的技术，而不会在涉及包括由可变电阻器和选择晶体管（CT）使用存储元件（RE）的存储器单元形成的存储单元阵列的相变存储器的制造设备中产生污染。 缓冲单元布置在读出放大器（SA）和存储单元阵列（MCA）之间以及字驱动器（WDB）和存储单元阵列之间。 缓冲单元由与存储单元相同的电阻存储元件（RE）和选择晶体管（CT）形成。 存储单元中的电阻存储元件通过形成在电阻存储元件上方的触点连接到位线。 同时，在缓冲单元中，电阻性存储元件之上不形成接触，并且在处理存储单元中的接触时保持被绝缘体覆盖的状态。 通过这种处理方法，可以避免在电阻存储元件中使用的硫族化物膜的曝光和升华。

公开(公告)号：US20120086070A1

公开(公告)日：2012-04-12

申请号：US13328104

申请日：2011-12-16

Applicant: Digh HISAMOTO ,  Shinichiro KIMURA ,  Kan YASUI ,  Nozomu MATSUZAKI

Inventor： Digh HISAMOTO ,  Shinichiro KIMURA ,  Kan YASUI ,  Nozomu MATSUZAKI

IPC: H01L29/792

CPC classification number: H01L27/11531 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/792

Abstract: A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

Abstract translation: 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

公开(公告)号：US20110309428A1

公开(公告)日：2011-12-22

申请号：US13223380

申请日：2011-09-01

Applicant: TOSHIHIRO TANAKA ,  Yukiko UMEMOTO ,  Mitsuru HIRAKI ,  Yutaka SHINAGAWA ,  Masamichi FUJITO ,  Kazufumi SUZUKAWA ,  Hiroyuki TANIKAWA ,  Takeshi YAMAKI ,  Yoshiaki KAMIGAKI ,  Shinichi MINAMI ,  Kozo KATAYAMA ,  Nozomu MATSUZAKI

Inventor： TOSHIHIRO TANAKA ,  Yukiko UMEMOTO ,  Mitsuru HIRAKI ,  Yutaka SHINAGAWA ,  Masamichi FUJITO ,  Kazufumi SUZUKAWA ,  Hiroyuki TANIKAWA ,  Takeshi YAMAKI ,  Yoshiaki KAMIGAKI ,  Shinichi MINAMI ,  Kozo KATAYAMA ,  Nozomu MATSUZAKI

IPC: H01L29/788

CPC classification number: G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

Abstract translation: 半导体器件包括多个非易失性存储单元（1）。 每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。 第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。 第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。 第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。 假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

公开(公告)号：US20110211390A1

公开(公告)日：2011-09-01

申请号：US12672685

申请日：2007-08-10

Applicant: Satoru Hanzawa ,  Fumihiko Nitta ,  Nozomu Matsuzaki ,  Toshihiro Tanaka

Inventor： Satoru Hanzawa ,  Fumihiko Nitta ,  Nozomu Matsuzaki ,  Toshihiro Tanaka

IPC: G11C11/00 ,  H01L21/8239

CPC classification number: G11C5/06 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144

Abstract: A technique capable of manufacturing a semiconductor device without posing contamination in a manufacturing apparatus regarding a phase change memory including a memory cell array formed of memory cells using a storage element (RE) by a variable resistor and a select transistor (CT). A buffer cell is arranged between a sense amplifier (SA) and a memory cell array (MCA) and between a word driver (WDB) and the memory cell array. The buffer cell is formed of the resistive storage element (RE) and the select transistor (CT) same as those of the memory cell. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.

Abstract translation: 一种能够制造半导体器件的技术，而不会在涉及包括由可变电阻器和选择晶体管（CT）使用存储元件（RE）的存储器单元形成的存储单元阵列的相变存储器的制造设备中产生污染。 缓冲单元布置在读出放大器（SA）和存储单元阵列（MCA）之间以及字驱动器（WDB）和存储单元阵列之间。 缓冲单元由与存储单元相同的电阻存储元件（RE）和选择晶体管（CT）形成。 存储单元中的电阻存储元件通过形成在电阻存储元件上方的触点连接到位线。 同时，在缓冲单元中，电阻性存储元件之上不形成接触，并且在处理存储单元中的接触时保持被绝缘体覆盖的状态。 通过这种处理方法，可以避免在电阻存储元件中使用的硫族化物膜的曝光和升华。

公开(公告)号：US07955872B2

公开(公告)日：2011-06-07

申请号：US12686954

申请日：2010-01-13

Applicant: Nozomu Matsuzaki

Inventor： Nozomu Matsuzaki

IPC: H01L21/00 ,  H01L21/20 ,  H01L21/8234 ,  H01L21/8244

CPC classification number: H01L27/228 ,  H01L43/12

Abstract: In the case where a laminated structure formed by laminating tunneling magnetoresistive films are processed by ion milling or the like, scattered substances of a material constituting the tunneling magnetoresistive film are deposited onto side walls of the laminated structure, or contaminate the inside of a device for processing. Accordingly, it has been difficult to manufacture a magnetic memory or a semiconductor device on which the magnetic memory is mounted, with stable characteristics.Side wall spacers are formed on side walls of a conductive layer arranged above a tunneling magnetoresistive film, and scattered substances of a material constituting the tunneling magnetoresistive film during processing are deposited. Thereafter, by removing the side wall spacers, the redepositions of the material are also removed. The side wall spacers used are of one kind or two kinds.

Abstract translation: 在通过层叠隧道磁阻膜形成的叠层结构通过离子铣削等进行处理的情况下，构成隧道磁阻膜的材料的散射物质沉积在层叠结构的侧壁上，或者污染装置的内部 处理。 因此，难以制造具有稳定特性的安装有磁性存储器的磁性存储器或半导体器件。 侧壁间隔物形成在布置在隧道磁阻膜上方的导电层的侧壁上，并且沉积在处理期间构成隧道磁阻膜的材料的散射物质。 此后，通过去除侧壁间隔物，材料的再沉积也被去除。 使用的侧壁垫片是一种或两种。

公开(公告)号：US07778069B2

公开(公告)日：2010-08-17

申请号：US12090458

申请日：2005-10-17

Applicant: Nozomu Matsuzaki ,  Kenichi Osada

Inventor： Nozomu Matsuzaki ,  Kenichi Osada

IPC: G11C11/00

CPC classification number: H01L27/105 ,  G11C11/005 ,  G11C13/0004 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

Abstract: An electrically rewritable non-volatile memory device is configured by the EEPROM 3, and an electrically non-rewritable non-volatile memory device is configured by the OTPROM 4a. Both the EEPROM 3 and the OTPROM 4a are configured by phase change memory devices each of which can be fabricated in the same fabrication step and at a low cost. The EEPROM3 uses a phase change memory device in which an amorphous state and a crystal state of a phase change material are used for memory information, while the OTPROM 4a uses a phase change memory device in which a non-disconnection state and a disconnection state of a phase change material are used for memory information.

Abstract translation: 电可重写非易失性存储器件由EEPROM 3配置，并且电不可重写的非易失性存储器件由OTPROM 4a配置。 EEPROM 3和OTPROM 4a都由相变存储器构成，每个相变存储器件可以在相同的制造步骤中以低成本制造。 EEPROM3使用相变材料的非晶状态和晶体状态用于存储器信息的相变存储器件，而OTPROM 4a使用相变存储器件，其中非断开状态和断开状态 相变材料用于存储器信息。

公开(公告)号：US07671404B2

公开(公告)日：2010-03-02

申请号：US11589095

申请日：2006-10-30

Applicant: Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

Inventor： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

IPC: H01L29/94

CPC classification number: H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

Abstract: A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

Abstract translation: 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

公开(公告)号：US20100012917A1

公开(公告)日：2010-01-21

申请号：US12302740

申请日：2006-05-31

Applicant: Norikatsu Takaura ,  Yuichi Matsui ,  Motoyasu Terao ,  Yoshihisa Fujisaki ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa

Inventor： Norikatsu Takaura ,  Yuichi Matsui ,  Motoyasu Terao ,  Yoshihisa Fujisaki ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa

IPC: H01L47/00

CPC classification number: G11C13/0004 ,  G11C8/08 ,  G11C13/0028 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

Abstract: On an insulating film (41) in which a plug (43) as a lower electrode is embedded, a laminated layer pattern of an insulating film (51) made of tantalum oxide, a recording layer (52) made of Ge—Sb—Te based chalcogenide to which indium is introduced and an upper electrode film (53) made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film (51) between the recording layer (52) and the plug (43), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer (52) can be achieved. Further, by using the Ge—Sb—Te based chalcogenide to which indium is introduced as the recording layer (52), the difference in work function between the insulating film (51) and the recording layer (52) is increased, and the programming voltage of the phase change memory can be reduced.

Abstract translation: 在嵌入作为下电极的插头（43）的绝缘膜（41）上，由氧化钽构成的绝缘膜（51）的叠层图案，由Ge-Sb-Te制成的记录层（52） 引入铟的硫属化合物和由钨或钨合金制成的上电极膜（53），从而形成相变存储器。 通过将绝缘膜（51）插入在记录层（52）和插塞（43）之间，可以实现降低相变存储器的编程电流的效果和防止记录层（52）的剥离的效果。 此外，通过使用引入了铟的Ge-Sb-Te类硫族化物作为记录层（52），绝缘膜（51）和记录层（52）之间的功函数差增大，编程 可以减小相变存储器的电压。