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    Method of forming a quantum dot and a gate electrode using the same
    81.
    发明授权
    Method of forming a quantum dot and a gate electrode using the same 有权
    使用该方法形成量子点和栅电极的方法

    公开(公告)号：US06756292B2

    公开(公告)日：2004-06-29

    申请号：US10243956

    申请日：2002-09-16

    Applicant: Jang-Eun Lee ,  Sun-Hoo Park ,  Jung-Hoon Son

    Inventor： Jang-Eun Lee ,  Sun-Hoo Park ,  Jung-Hoon Son

    IPC: H01L21477

    CPC classification number: B82Y20/00 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10873 ,  Y10S438/962

    Abstract: In a method of forming a quantum dot having nanometeric size and a method of forming a gate electrode including the quantum dot, a first layer including a first material is deposited on the substrate. The first material has first atoms that are superbundant and bound with the weak bonding energy in the first layer. A second layer is deposited on the first layer. The second layer comprises a second material including second atoms that are capable of migrating into the first atoms. The first atoms are migrated into the second layer and the second atoms are migrated into the first layer, so that the second atoms are arranged in the first layer. Each of the second atoms in the first layer is formed into a quantum dot. An electrode layer is formed on the first layer after partially etching the second layer, and then a gate electrode is formed by patterning the electrode layer. Accordingly, The quantum dot can be formed in the semiconductor device in such a manner that a size and a distribution of the quantum dot is easily controlled.

    Abstract translation: 在形成具有纳米尺寸的量子点的方法和形成包括量子点的栅电极的方法中，在基板上沉积包括第一材料的第一层。 第一种材料具有超第一原子，并与第一层中的弱键合能结合。 第二层沉积在第一层上。 第二层包括第二材料，其包括能够迁移到第一原子中的第二原子。 第一原子迁移到第二层中，第二原子迁移到第一层中，使得第二原子排列在第一层中。 第一层中的每个第二原子形成量子点。 在部分蚀刻第二层之后，在第一层上形成电极层，然后通过图案化电极层形成栅电极。 因此，可以以量子点的尺寸和分布容易地控制的方式在半导体器件中形成量子点。

    Methods of forming pattern structures
    83.
    发明授权
    Methods of forming pattern structures 有权
    形成图案结构的方法

    公开(公告)号：US08334148B2

    公开(公告)日：2012-12-18

    申请号：US13184127

    申请日：2011-07-15

    Applicant: Jun-Ho Jeong ,  Jang-Eun Lee ,  Woo-Jin Kim ,  Hee-Ju Shin ,  Yong-Hwan Ryu

    Inventor： Jun-Ho Jeong ,  Jang-Eun Lee ,  Woo-Jin Kim ,  Hee-Ju Shin ,  Yong-Hwan Ryu

    IPC: H01L21/00

    CPC classification number: H01L27/228 ,  H01L43/12

    Abstract: An example embodiment relates to a method of forming a pattern structure, including forming an object layer on a substrate, and forming a hard mask on the object layer. A plasma reactive etching process is performed on the object layer using an etching gas including a fluorine containing gas and ammonia (NH3) gas together with oxygen gas to form a pattern. The oxygen gas is used for suppressing the removal of the hard mask during the etching process.

    Abstract translation: 示例性实施例涉及一种形成图案结构的方法，包括在基底上形成物体层，并在物体层上形成硬掩模。 使用包含含氟气体和氨（NH 3）气体的蚀刻气体与氧气一起在物体层上进行等离子体反应蚀刻工艺以形成图案。 氧气用于在蚀刻过程中抑制硬掩模的去除。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    84.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20110189851A1

    公开(公告)日：2011-08-04

    申请号：US13016228

    申请日：2011-01-28

    Applicant: Jun-Ho JEONG ,  Jang-Eun Lee ,  Se-Chung Oh ,  Suk-Hun Choi ,  Jea-Hyoung Lee ,  Woo-Jin Kim ,  Woo-Chang Lim

    Inventor： Jun-Ho JEONG ,  Jang-Eun Lee ,  Se-Chung Oh ,  Suk-Hun Choi ,  Jea-Hyoung Lee ,  Woo-Jin Kim ,  Woo-Chang Lim

    IPC: H01L21/28

    CPC classification number: H01L21/28

    Abstract: A method of fabricating a semiconductor device, the method including providing a substrate; forming an underlying layer on the substrate; forming a sacrificial layer on the underlying layer; forming an opening in the sacrificial layer by patterning the sacrificial layer such that the opening exposes a predetermined region of the underlying layer; forming a mask layer in the opening; forming an oxide mask by partially or completely oxidizing the mask layer; removing the sacrificial layer; and etching the underlying layer using the oxide mask as an etch mask to form an underlying layer pattern.

    Abstract translation: 一种制造半导体器件的方法，所述方法包括提供衬底; 在衬底上形成下层; 在下层上形成牺牲层; 通过图案化所述牺牲层在所述牺牲层中形成开口，使得所述开口暴露所述下层的预定区域; 在开口中形成掩模层; 通过部分或完全氧化掩模层形成氧化物掩模; 去除牺牲层; 并使用氧化物掩模作为蚀刻掩模蚀刻下层，以形成下层图案。

    Magnetic Memory Device
    85.
    发明申请
    Magnetic Memory Device 有权
    磁存储器件

    公开(公告)号：US20100213558A1

    公开(公告)日：2010-08-26

    申请号：US12773451

    申请日：2010-05-04

    Applicant: Jun-Soo Bae ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  Se-Chung Oh ,  Kyung-Tae Nam

    Inventor： Jun-Soo Bae ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  Se-Chung Oh ,  Kyung-Tae Nam

    IPC: H01L29/82

    CPC classification number: G11C11/15 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3254 ,  H01F10/3272 ,  H01F10/3281 ,  H01F41/302 ,  H01L43/08

    Abstract: A magnetic memory device is provided. The magnetic memory device includes an invariable pinning pattern and a variable pinning pattern on a substrate. A tunnel barrier pattern is interposed between the invariable pinning pattern and the variable pinning pattern, and the pinned pattern is interposed between the invariable pinning pattern and the tunnel barrier pattern. A storage free pattern is interposed between the tunnel barrier pattern and the variable pinning pattern, and a guide free pattern is interposed between the storage free pattern and the variable pinning pattern. A free reversing pattern is interposed between the storage and guide free patterns. The free reversing pattern reverses a magnetization direction of the storage free pattern and a magnetization direction of the guide free pattern in the opposite directions.

    Abstract translation: 提供磁存储器件。 磁存储器件在衬底上包括不变的钉扎图案和可变的钉扎图案。 在不变的钉扎图案和可变钉扎图案之间插入隧道势垒图案，并且钉扎图案介于不变钉扎图案和隧道屏障图案之间。 在隧道势垒图案和可变钉扎图案之间插入无存储图案，并且在存储空闲图案和可变钉扎图案之间插入无引导图案。 在存储和无引导模式之间插入一个自由的反转模式。 自由反转图案反转无存储图案的磁化方向和反向自由图案的磁化方向。

    Magnetic random access memory device and method of forming the same
    87.
    发明授权
    Magnetic random access memory device and method of forming the same 有权
    磁性随机存取存储器件及其形成方法

    公开(公告)号：US07372090B2

    公开(公告)日：2008-05-13

    申请号：US11347280

    申请日：2006-02-06

    Applicant: Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Soo Bae ,  Hyun-Jo Kim ,  Kyung-Tae Nam ,  Young-Ki Ha

    Inventor： Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Soo Bae ,  Hyun-Jo Kim ,  Kyung-Tae Nam ,  Young-Ki Ha

    IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC classification number: G11C11/16 ,  B82Y10/00 ,  B82Y25/00 ,  G11B5/3909 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12 ,  Y10T29/49034 ,  Y10T29/49044

    Abstract: Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a magnetic tunnel junction (MTJ) pattern disposed on the intermediate insulating layer and over the digit line, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., and a bit line connected to the capping pattern and disposed to intersect the digit line. A method of forming a semiconductor memory device may include forming a digit line on a substrate, forming an intermediate insulating layer covering the digit line, forming a magnetic tunnel junction (MTJ) pattern on the intermediate insulating layer, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., performing an annealing operation at a temperature of about 350° C. or higher, and forming a bit line connected to the capping pattern and disposed to intersect the digit line.

    Abstract translation: 本发明的示例性实施例公开了半导体存储器件和形成存储器件的方法。 半导体存储器件可以包括设置在衬底上的数字线，覆盖数字线的中间绝缘层，设置在中间绝缘层上方和数字线上的磁性隧道结（MTJ）图案，MTJ图案包括顺序堆叠 下磁性图案，上磁性图案和封盖图案，其中封盖图案在高于约280℃的温度下不与上磁性图案反应，而位线连接到封盖图案并且设置成与数字线相交 。 形成半导体存储器件的方法可以包括在衬底上形成数字线，形成覆盖数字线的中间绝缘层，在中间绝缘层上形成磁隧道结（MTJ）图案，MTJ图案包括顺序层叠的 较低的磁性图案，上部磁性图案和封盖图案，其中封盖图案在高于约280℃的温度下不与上部磁性图案反应，在约350℃或更高的温度下进行退火操作， 并且形成连接到所述封盖图案并且设置成与所述数字线相交的位线。

    Magnetic tunnel junction structure having an oxidized buffer layer and method of fabricating the same
    90.
    发明授权
    Magnetic tunnel junction structure having an oxidized buffer layer and method of fabricating the same 有权
    具有氧化缓冲层的磁隧道结结构及其制造方法

    公开(公告)号：US07141438B2

    公开(公告)日：2006-11-28

    申请号：US10915872

    申请日：2004-08-10

    Applicant: Young-Ki Ha ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  Se-Chung Oh ,  Jun-Soo Bae ,  In-Gyu Baek

    Inventor： Young-Ki Ha ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  Se-Chung Oh ,  Jun-Soo Bae ,  In-Gyu Baek

    IPC: H01L21/00

    CPC classification number: H01L43/12 ,  H01L43/08

    Abstract: There are provided a magnetic tunnel junction structure and a method of fabricating the same. The magnetic tunnel junction structure includes a lower electrode, a lower magnetic layer pattern and a tunnel layer pattern, which are sequentially formed on the lower electrode. The magnetic tunnel junction structure further includes an upper magnetic layer pattern, a buffer layer pattern, and an upper electrode, which are sequentially formed on a portion of the tunnel layer pattern. The sidewall of the upper magnetic layer pattern is surrounded by an oxidized upper magnetic layer, and the sidewall of the buffer layer pattern is surrounded by an oxidized buffer layer. The depletion of the upper magnetic layer pattern and the lower magnetic layer pattern in the magnetic tunnel junction region can be prevented by the oxidized buffer layer.

    Abstract translation: 提供了一种磁性隧道结结构及其制造方法。 磁性隧道结结构包括依次形成在下电极上的下电极，下磁层图案和隧道层图案。 磁隧道结结构还包括依次形成在隧道层图案的一部分上的上磁层图案，缓冲层图案和上电极。 上部磁性层图案的侧壁由氧化的上部磁性层包围，缓冲层图案的侧壁由氧化的缓冲层包围。 可以通过氧化缓冲层来防止磁性隧道结区域中上部磁性层图案和下部磁性层图案的消耗。

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