公开(公告)号：US07732328B2

公开(公告)日：2010-06-08

申请号：US11866942

申请日：2007-10-03

Applicant: Yong-Chai Kwon ,  Dong-Ho Lee

Inventor： Yong-Chai Kwon ,  Dong-Ho Lee

IPC: H01L21/44 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/5258 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05569 ,  H01L2224/13008 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A semiconductor package structure and a method of fabricating the same are disclosed. A method of fabricating the semiconductor package structure can be characterized as including forming semiconductor chips on a semiconductor substrate. Each of the semiconductor chips includes chip pads. Through-vias are formed through the semiconductor chips. Redistribution structures and a chip selection interconnection layer are formed on the semiconductor chips, which connect the through-vias with the chip pads. The chip selection interconnection layers are patterned to form chip selection interconnection lines having different structures on at least one of the semiconductor chips. The semiconductor chips are stacked and electrically connected using the through-vias.

Abstract translation: 公开了一种半导体封装结构及其制造方法。 制造半导体封装结构的方法可以表征为包括在半导体衬底上形成半导体芯片。 每个半导体芯片包括芯片焊盘。 通孔通过半导体芯片形成。 重新分配结构和芯片选择互连层形成在将通孔与芯片焊盘连接的半导体芯片上。 芯片选择互连层被图案化以在至少一个半导体芯片上形成具有不同结构的芯片选择互连线。 半导体芯片使用贯通孔堆叠并电连接。

公开(公告)号：US07644936B2

公开(公告)日：2010-01-12

申请号：US11606466

申请日：2006-11-29

Applicant: Dong-Ho Lee

Inventor： Dong-Ho Lee

IPC: B60G3/26

CPC classification number: B62D17/00 ,  B60G7/006 ,  B60G2200/10 ,  B60G2200/464 ,  B60G2202/413 ,  B60G2204/148 ,  B60G2204/416 ,  B60G2204/4232 ,  B60G2204/62 ,  B60G2600/182 ,  B60G2800/24

Abstract: Disclosed is a caster control apparatus for a suspension of a vehicle. When the vehicle travels on a road which causes a vehicle body to lean to one side, the caster of a lowered wheel is increased, and the caster of a raised wheel is decreased, such that the casters of the wheels on both sides are offset with each other. Therefore, the vehicle is inhibited from leaning due to the lateral slope of the road, and the straight-line stability of the vehicle can be reliably maintained.

Abstract translation: 公开了一种用于车辆悬架的脚轮控制装置。 当车辆在导致车体倾斜到一侧的道路上行驶时，下轮的脚轮增加，并且升轮的脚轮减小，使得两侧的车轮的脚轮偏移 彼此。 因此，由于道路的横向倾斜，车辆被阻止倾斜，能够可靠地保持车辆的直线稳定性。

公开(公告)号：US07636654B2

公开(公告)日：2009-12-22

申请号：US11260159

申请日：2005-10-28

Applicant: Songcheol Hong ,  Dong Ho Lee ,  Kyung-Ai Lee

Inventor： Songcheol Hong ,  Dong Ho Lee ,  Kyung-Ai Lee

IPC: G06F17/50

CPC classification number: H03F3/45 ,  H03F2203/45361

Abstract: A differential amplifier and a method for generating a computer simulation model thereof are disclosed. The device is thermally stable through adoption of a ballast resistor to a differential structure of a unit transistor pair, such that the differential amplifier prevents heat effect phenomena, such as performance deterioration and device destruction by heating, and, at the same time, improves or maintains other performances, thereby achieving high gain, high efficiency, high linearity, and wide bandwidth characteristics. Therefore, the differential amplifier can be easily designed as undesired effects of parasitic resistor of emitter or via or bonding wire, etc. for the differential amplifier are reduced in a differential mode.

Abstract translation: 公开了一种差分放大器及其计算机仿真模型的生成方法。 该器件通过对单位晶体管对的差分结构采用镇流电阻器而具有热稳定性，使得差分放大器防止诸如性能恶化和器件通过加热破坏的热效应现象，并且同时改善或 保持其他性能，从而实现高增益，高效率，高线性度和宽带宽特性。 因此，差分放大器可以很容易地设计为差分放大器的寄生电阻器的不期望的效应，差分放大器在差分模式下减小。

公开(公告)号：US20090284423A1

公开(公告)日：2009-11-19

申请号：US12465416

申请日：2009-05-13

Applicant: Kyung-Hack YI ,  Dong-Ho Lee

Inventor： Kyung-Hack YI ,  Dong-Ho Lee

IPC: H01Q1/24 ,  H01Q1/38

CPC classification number: H01Q1/2283 ,  H01Q1/243 ,  H01Q1/38 ,  H01Q7/08

Abstract: A portable terminal with an antenna for receiving broadcast signals, includes an antenna module having a chip antenna patterned on a dielectric chip so as to define a physical length of the antenna module that enables the chip antenna to operate within a broadcast band, and a conductive plate connected to the chip antenna and having an area such that conductive plate leads a main radiation of the antenna module on the broadcast band, whereby the physical length of the antenna module can be reduced as short as possible by employing the chip antenna. Accordingly, the chip antenna facilitates making the antenna module and the portable terminal be smaller in size. Also, the chip antenna is configured to lead a main radiation on the conductive plate, thereby increasing radio reception quality and improving radio performance.

Abstract translation: 具有用于接收广播信号的天线的便携式终端包括天线模块，其具有图案化在介质芯片上的芯片天线，以便限定天线模块的物理长度，使得芯片天线能够在广播频带内工作，并且导电 连接到芯片天线的板，并且具有使得导电板在广播频带上引导天线模块的主辐射的区域，由此可以通过采用芯片天线尽可能地减小天线模块的物理长度。 因此，芯片天线有助于使天线模块和便携式终端的尺寸更小。 此外，芯片天线被配置为引导导电板上的主辐射，从而增加无线电接收质量并提高无线电性能。

公开(公告)号：US07602047B2

公开(公告)日：2009-10-13

申请号：US11979562

申请日：2007-11-06

Applicant: Yong-Chai Kwon ,  Dong-Ho Lee ,  In-Young Lee

Inventor： Yong-Chai Kwon ,  Dong-Ho Lee ,  In-Young Lee

IPC: H01L29/40

CPC classification number: H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A method of fabricating a semiconductor device is provided. The method may include forming an insulating layer on a wafer. The wafer may have an active surface and an inactive surface which face each other, and the insulating layer may be formed on the active surface. A pad may be formed on the insulating layer, and a first hole may be formed in the insulating layer. A first hole insulating layer may then be formed on an inner wall of the first hole. A second hole may be formed under the first hole. The second hole may be formed to extend from the first hole into the wafer. A second hole insulating layer may be formed on an inner wall of the second hole. The semiconductor device fabricated according to the method may also be provided.

Abstract translation: 提供一种制造半导体器件的方法。 该方法可以包括在晶片上形成绝缘层。 晶片可以具有彼此面对的有源表面和非活性表面，并且绝缘层可以形成在有源表面上。 可以在绝缘层上形成焊盘，并且可以在绝缘层中形成第一孔。 然后可以在第一孔的内壁上形成第一孔绝缘层。 可以在第一孔下方形成第二孔。 第二孔可以形成为从第一孔延伸到晶片。 第二孔绝缘层可以形成在第二孔的内壁上。 还可以提供根据该方法制造的半导体器件。

公开(公告)号：US07588964B2

公开(公告)日：2009-09-15

申请号：US11790173

申请日：2007-04-24

Applicant: Yong-Chai Kwon ,  Dong-Ho Lee ,  Myung-Kee Chung ,  Kang-Wook Lee ,  Sun-Won Kang ,  Keum-Hee Ma

Inventor： Yong-Chai Kwon ,  Dong-Ho Lee ,  Myung-Kee Chung ,  Kang-Wook Lee ,  Sun-Won Kang ,  Keum-Hee Ma

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/12 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/90 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/83856 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A stacked structure of semiconductor devices may include a plurality of stacked semiconductor devices, each having an upper surface and a lower surface and one or more via electrodes protruding from the upper surface to the lower surface. The via-electrodes may have upper parts (heads) protruding from the upper surface and lower parts (ends) protruding from the lower surface. The stacked semiconductor devices may be electrically connected to each other through the via-electrodes. A first adhesive film (e.g., patternable material) and a second adhesive film (e.g. puncturable material) may be formed between the stacked semiconductor devices. The stacked structure of semiconductor devices may be mounted on the upper surface of a printed circuit board (PCB) having a mount-specific adhesive film to form a semiconductor device package. The mounted stacked structure and the upper surface of the PCB may be further covered with a molding material.

Abstract translation: 半导体器件的层叠结构可以包括多个层叠的半导体器件，每个具有上表面和下表面以及从上表面到下表面突出的一个或多个通孔电极。 通孔电极可以具有从上表面突出的上部（头）和从下表面突出的下部（端部）。 层叠的半导体器件可以通过通孔电极彼此电连接。 可以在层叠的半导体器件之间形成第一粘合膜（例如，可图案化材料）和第二粘合膜（例如可刺穿材料）。 半导体器件的堆叠结构可以安装在具有安装专用粘合剂膜的印刷电路板（PCB）的上表面上以形成半导体器件封装。 安装的堆叠结构和PCB的上表面可以进一步被模制材料覆盖。

公开(公告)号：US20090079496A1

公开(公告)日：2009-03-26

申请号：US12238894

申请日：2008-09-26

Applicant: Byung-Se SO ,  Dong-Ho LEE ,  Hyun-Soon JANG

Inventor： Byung-Se SO ,  Dong-Ho LEE ,  Hyun-Soon JANG

IPC: H01L25/00 ,  H05K7/00

CPC classification number: H01L24/49 ,  G11C5/00 ,  G11C5/06 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01055 ,  H01L2924/01075 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed. Also, when a signal that is not necessarily transmitted at high speed is applied to a pin, semiconductor chips can be packaged according to the preexisting methods.

Abstract translation: 多芯片封装包括第一至第N个半导体芯片，每个半导体芯片包括输入/​​输出焊盘，耦合到输入/输出焊盘的输入/输出驱动器和内部电路。 第一至第N半导体芯片中的每一个包括用于耦合内部输入/输出驱动器和内部电路的内部焊盘。 第一至第N半导体芯片的内部焊盘彼此耦合，例如经由安装在基板上的公共焊盘。 第一半导体芯片的输入/输出焊盘直接接收通过多芯片封装的相应引脚传输的输入/输出信号。 第二至第N半导体芯片通过彼此耦合的内部焊盘间接接收输入/输出信号。 当信号以高速传输到引脚时，多芯片封装可以通过将引脚的寄生负载保持在至少单个芯片的电平来提高信号兼容性。 此外，当不需要高速传输的信号被施加到引脚时，可以根据预先存在的方法来封装半导体芯片。

公开(公告)号：US20090065950A1

公开(公告)日：2009-03-12

申请号：US12267343

申请日：2008-11-07

Applicant: Jong-Joo LEE ,  Dong-Ho LEE

Inventor： Jong-Joo LEE ,  Dong-Ho LEE

IPC: H01L23/52

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/66 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided are a stack chip and a stack chip package having the stack chip. Internal circuits of two semiconductor chips are electrically connected to each other through an input/output buffer connected to an external connection terminal. The semiconductor chip has chip pads, input/output buffers and internal circuits connected through circuit wirings. The semiconductor chip also has connection pads connected to the circuit wirings connecting the input/output buffers to the internal circuits. The semiconductor chips include a first chip and a second chip. The connection pads of the first chip are electrically connected to the connection pads of the second chip through electrical connection means. Input signals input through the external connection terminals are input to the internal circuits of the first chip or the second chip via the chip pads and the input/output buffers of the first chip, and the connection pads of the first chip and the second chip.

Abstract translation: 提供了具有堆叠芯片的堆叠芯片和堆叠芯片封装。 两个半导体芯片的内部电路通过连接到外部连接端子的输入/输出缓冲器彼此电连接。 半导体芯片具有芯片焊盘，输入/输出缓冲器和通过电路布线连接的内部电路。 半导体芯片还具有连接到将输入/输出缓冲器连接到内部电路的电路布线的连接焊盘。 半导体芯片包括第一芯片和第二芯片。 第一芯片的连接焊盘通过电连接装置电连接到第二芯片的连接焊盘。 通过外部连接端子输入的输入信号经由芯片焊盘和第一芯片的输入/输出缓冲器以及第一芯片和第二芯片的连接焊盘输入到第一芯片或第二芯片的内部电路。

公开(公告)号：US20090036328A1

公开(公告)日：2009-02-05

申请号：US12179219

申请日：2008-07-24

Applicant: June-Young LEE ,  Dong-Ho LEE

Inventor： June-Young LEE ,  Dong-Ho LEE

IPC: C40B60/12

CPC classification number: C40B60/12 ,  B01L3/508 ,  B01L2200/16 ,  B01L2300/047 ,  B01L2300/0636

Abstract: A biochip package allowing biochips optimized for high-volume production to be compatible with general-purpose devices and a biochip packaging substrate of the biochip package are provided. The biochip package can include a biochip having a probe array mounted thereon and a biochip packaging substrate on which the biochip is mounted and which has a through cavity exposing a rear surface of the biochip.

Abstract translation: 提供了一种生物芯片封装，允许针对大批量生产优化的生物芯片与通用器件和生物芯片封装的生物芯片封装衬底兼容。 生物芯片封装可以包括其上安装有探针阵列的生物芯片和其上安装有生物芯片的生物芯片封装衬底，并且具有暴露生物芯片后表面的通孔。

公开(公告)号：US20090032966A1

公开(公告)日：2009-02-05

申请号：US12222004

申请日：2008-07-31

Applicant: Jong Ho Lee ,  Dong Ho Lee ,  Eun Chul Ahn ,  Yong Chai Kwon

Inventor： Jong Ho Lee ,  Dong Ho Lee ,  Eun Chul Ahn ,  Yong Chai Kwon

IPC: H01L23/52 ,  H01L21/00 ,  H01L21/44

CPC classification number: H01L21/76898 ,  H01L23/525 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having an active surface, thinning the substrate by removing material from a second surface of the substrate opposite the active surface, bonding a metal carrier to the second surface of the thinned substrate, forming a via opening in the thinned substrate, forming a conductive member in the via opening, and patterning the metal carrier bonded to the second surface of the thinned substrate to form a metal pattern.

Abstract translation: 一种制造半导体器件的方法包括提供具有活性表面的半导体衬底，通过从衬底的与活性表面相对的第二表面去除材料来稀释衬底，将金属载体接合到薄化衬底的第二表面上，形成 通过在所述薄化基板中的开口，在所述通孔开口中形成导电构件，并且图案化结合到所述薄化基板的第二表面的金属载体以形成金属图案。