公开(公告)号：US20090186777A1

公开(公告)日：2009-07-23

申请号：US12357270

申请日：2009-01-21

Applicant: June-Young LEE ,  Dong-Ho LEE ,  Jae-Young KIM

Inventor： June-Young LEE ,  Dong-Ho LEE ,  Jae-Young KIM

IPC: C40B40/04

CPC classification number: C40B99/00 ,  B01J19/0046 ,  B01J2219/00317 ,  B01J2219/00527 ,  B01J2219/00596 ,  B01J2219/00605 ,  B01J2219/00617 ,  B01J2219/00621 ,  B01J2219/00626 ,  B01J2219/00637 ,  B01J2219/00659 ,  B01J2219/00662 ,  B01J2219/0072 ,  B01L3/5085 ,  B01L2200/10 ,  B01L2200/12 ,  B01L2300/0636 ,  B01L2300/0829 ,  B01L2300/0893

Abstract: A biochip can include a substrate having surface features of protrusions or recesses and probes coupled to each of the surface features. A biochip can include a substrate having recess regions and probes coupled to each of the recess regions, wherein a surface of each of the recess regions has convexes and concaves. A biochip can include a substrate having recess regions, immobilization layers conformally formed in the recess regions, and probes coupled onto each of the immobilization layers. The biochip can be divided into probe cell regions to which the probes are coupled, wherein the recess regions are formed in the probe cell regions, and non-probe cell regions, wherein a surface of each of the non-probe cell regions can include an exposed surface of the substrate.

Abstract translation: 生物芯片可以包括具有突起或凹陷的表面特征的基底和耦合到每个表面特征的探针。 生物芯片可以包括具有凹陷区域的衬底和耦合到每个凹陷区域的探针，其中每个凹陷区域的表面具有凸起和凹陷。 生物芯片可以包括具有凹陷区域的基底，在凹陷区域中保形地形成的固定层，以及耦合到每个固定层上的探针。 生物芯片可以分为与探针连接的探针细胞区域，其中在探针细胞区域中形成凹陷区域，以及非探针细胞区域，其中每个非探针细胞区域的表面可以包括 曝光的表面。

公开(公告)号：US20090036328A1

公开(公告)日：2009-02-05

申请号：US12179219

申请日：2008-07-24

Applicant: June-Young LEE ,  Dong-Ho LEE

Inventor： June-Young LEE ,  Dong-Ho LEE

IPC: C40B60/12

CPC classification number: C40B60/12 ,  B01L3/508 ,  B01L2200/16 ,  B01L2300/047 ,  B01L2300/0636

Abstract: A biochip package allowing biochips optimized for high-volume production to be compatible with general-purpose devices and a biochip packaging substrate of the biochip package are provided. The biochip package can include a biochip having a probe array mounted thereon and a biochip packaging substrate on which the biochip is mounted and which has a through cavity exposing a rear surface of the biochip.

Abstract translation: 提供了一种生物芯片封装，允许针对大批量生产优化的生物芯片与通用器件和生物芯片封装的生物芯片封装衬底兼容。 生物芯片封装可以包括其上安装有探针阵列的生物芯片和其上安装有生物芯片的生物芯片封装衬底，并且具有暴露生物芯片后表面的通孔。

公开(公告)号：US20080159919A1

公开(公告)日：2008-07-03

申请号：US11946770

申请日：2007-11-28

Applicant: June-Young LEE ,  Dong-Ho LEE

Inventor： June-Young LEE ,  Dong-Ho LEE

IPC: B01L11/00 ,  G01N33/566

CPC classification number: B01L3/508 ,  B01L1/52 ,  B01L2200/026 ,  B01L2300/045 ,  B01L2300/0636 ,  B01L2300/0809

Abstract: Provided is a biochip kit and a method capable of detecting the binding of target molecules in a biological sample to at least one probe on a biochip. The biochip kit includes a housing, a biochip, disposed in the housing, including at least one probe, and a lid, connectedly installed on the housing, such that the lid can open or close the housing.

Abstract translation: 提供了一种生物芯片试剂盒和能够检测生物样品中的靶分子与生物芯片上的至少一种探针的结合的方法。 生物芯片套件包括壳体，生物芯片，设置在壳体中，包括至少一个探针和连接安装在壳体上的盖，使得盖可以打开或关闭壳体。

公开(公告)号：US20120207167A1

公开(公告)日：2012-08-16

申请号：US13457402

申请日：2012-04-26

Applicant: Seung-Ho SEO ,  Hae-Eun MOON ,  Dong-Ho LEE

Inventor： Seung-Ho SEO ,  Hae-Eun MOON ,  Dong-Ho LEE

IPC: H04L12/56

CPC classification number: H04L41/12 ,  H04L45/02

Abstract: A method of searching for a host in a network using IPv4 network comprises the steps of requesting host information, including link-layer address information and IP address information about an IP to be searched for, by sending a Neighbor Solicitation (NS) packet in which the IP to be searched for is set in an ICMPv6 target address to the network, after sending the NS packet, waiting for a predetermined time by taking a processing speed of a host and a transfer rate according to a network environment and state into consideration, after the predetermined time of waiting, determining whether a Neighbor Advertisement (NA) packet of the IP to be searched for has been received, and if, as a result of the determination, the NA packet of the IP to be searched for is determined to have been received, acquiring the host information from the NA packet.

Abstract translation: 使用IPv4网络在网络中搜索主机的方法包括以下步骤：通过发送邻居请求（NS）分组来请求包括链路层地址信息和关于要搜索的IP的IP地址信息的主机信息，其中， 要搜索的IP被设置在ICMPv6目标地址中，在发送NS分组之后，根据网络环境和状态考虑主机的处理速度和传输速率等待预定时间， 在预定的等待时间之后，确定是否已经接收到要搜索的IP的邻居广播（NA）分组，并且如果作为确定的结果，将要搜索的IP的NA分组被确定为 已经接收到，从NA分组获取主机信息。

公开(公告)号：US20060226543A1

公开(公告)日：2006-10-12

申请号：US11424055

申请日：2006-06-14

Applicant: Jung-Jin KIM ,  Young-Hee SONG ,  Dong-Ho LEE

Inventor： Jung-Jin KIM ,  Young-Hee SONG ,  Dong-Ho LEE

IPC: H01L23/48

CPC classification number: H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Disclosed herein is a ball grid array (BGA) package stack that is not limited by ball arrangement because it utilizes a foldable circuit substrate, which permits interconnection between upper and lower individual BGA packages. The foldable circuit substrate has three portions. By bending the middle second portion, the foldable circuit substrate is folded in two. In the lower BGA package, an IC chip is attached on and electrically connected to a top surface of the first portion, and external connection terminals such as solder balls are formed on a bottom surface of the first portion. The top surface of the first portion is covered with a molding resin to protect the chip, and the third portion is placed on an upper surface of the molding resin. The upper BGA package is constructed in a similar manner to the lower BGA package as described above. For stacking, the interconnection terminals of the upper BGA package are joined and electrically connected to the third portion of the foldable circuit substrate of the lower BGA package.

Abstract translation: 本文公开了一种球栅阵列（BGA）封装堆叠，其不受球布置的限制，因为它使用可折叠电路基板，其允许上部和下部单个BGA封装之间的互连。 可折叠电路基板具有三个部分。 通过弯曲中间第二部分，可折叠电路基板折叠成两个。 在较低的BGA封装中，IC芯片附着在电连接到第一部分的顶表面上，并且在第一部分的底表面上形成诸如焊球的外部连接端子。 第一部分的顶表面被模制树脂覆盖以保护芯片，并且第三部分被放置在模制树脂的上表面上。 上部BGA封装以与上述较低BGA封装类似的方式构造。 为了堆叠，上部BGA封装的互连端子被接合并电连接到下部BGA封装的可折叠电路基板的第三部分。

公开(公告)号：US20110298902A1

公开(公告)日：2011-12-08

申请号：US12962406

申请日：2010-12-07

Applicant: So-Young KIM ,  Seung-Ho AHN ,  Dong-Ho LEE

Inventor： So-Young KIM ,  Seung-Ho AHN ,  Dong-Ho LEE

IPC: H04N13/04 ,  G02B26/02

CPC classification number: G02B27/2264 ,  G02B27/2242 ,  H04N13/341 ,  H04N2213/008

Abstract: Provided are a shutter glasses for a 3D image display, a 3D image display system including the same, and a manufacturing method thereof. Shutter glasses for a 3D image display system according to an exemplary embodiment of the present invention include a left eye shutter and a right eye shutter. At least one of the left eye shutter and the right eye shutter includes a MEMS element controlling an opening and a closing of the at least one of the left eye shutter and the right eye shutter.

Abstract translation: 提供了一种用于3D图像显示器的快门眼镜，包括其的3D图像显示系统及其制造方法。 根据本发明的示例性实施例的用于3D图像显示系统的快门眼镜包括左眼快门和右眼快门。 左眼快门和右眼快门中的至少一个包括控制左眼快门和右眼快门中的至少一个的开口和关闭的MEMS元件。

公开(公告)号：US20110194064A1

公开(公告)日：2011-08-11

申请号：US13088839

申请日：2011-04-18

Applicant: Dong-Ho LEE

Inventor： Dong-Ho LEE

IPC: G02F1/1339

CPC classification number: G02F1/13454 ,  G02F1/133345 ,  G02F1/1339 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2203/09

Abstract: An LCD device provides enhanced display quality. An insulating layer is formed on a first substrate. The insulating layer covers the contact portion of a switching device in which the switching device is electrically connected to a transparent electrode and has an opening for exposing a portion of the transparent electrode. A reflection electrode is electrically connected to the transparent electrode through the opening. The insulation layer covers a first portion of a driving circuit formed on the first substrate. A sealant is interposed between the first and second substrate to engage the first and second substrate and to cover a second portion of the driving circuit. Therefore, the driver circuit may operate normally, and the distortion of the signal outputted from the driver circuit may be prevented.

公开(公告)号：US20090168382A1

公开(公告)日：2009-07-02

申请号：US12344817

申请日：2008-12-29

Applicant: Hyun-Soo CHUNG ,  Dong-Ho LEE ,  Dong-Han KIM ,  Seong-Deok HWANG ,  Ki-Hyuk KIM

Inventor： Hyun-Soo CHUNG ,  Dong-Ho LEE ,  Dong-Han KIM ,  Seong-Deok HWANG ,  Ki-Hyuk KIM

IPC: H05K7/06

CPC classification number: H05K1/185 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H05K3/3457 ,  H05K3/4694 ,  H05K2201/10719

Abstract: A semiconductor module can include a printed circuit board (PCB) and a semiconductor package inserted into an inner space of the PCB. The semiconductor package may be electrically connected to the PCB. The PCB may thus surround the semiconductor package so that cracks may not be generated in the outer terminals.

Abstract translation: 半导体模块可以包括插入到PCB的内部空间中的印刷电路板（PCB）和半导体封装。 半导体封装可以电连接到PCB。 因此，PCB可以围绕半导体封装，从而可能不会在外部端子中产生裂纹。

公开(公告)号：US20080179727A1

公开(公告)日：2008-07-31

申请号：US11852930

申请日：2007-09-10

Applicant: Yong-Chai KWON ,  Keum-Hee MA ,  Dong-Ho LEE ,  Kang-Wook LEE

Inventor： Yong-Chai KWON ,  Keum-Hee MA ,  Dong-Ho LEE ,  Kang-Wook LEE

IPC: H01L23/02 ,  H01L21/00

CPC classification number: H01L25/50 ,  H01L23/147 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/24051 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14

Abstract: Provided are semiconductor packages having immunity against a void due to an adhesive material and methods of fabricating the same. The semiconductor packages and the methods of fabricating the same can eliminate voids between package bodies to minimize delamination of the package bodies from the semiconductor package during the life time of semiconductor devices. To this end, a circuit substrate, a controller, and package bodies may be prepared. Each of the package bodies may have a package substrate, an adhesive pattern, and a package insulating layer. The package insulating layer may be formed on the package substrate to surround the adhesive pattern. The package bodies may be formed between the controller and the circuit substrate and contact the controller and the circuit substrate.

Abstract translation: 提供了由于粘合剂材料而具有对空隙的抗扰性的半导体封装及其制造方法。 半导体封装及其制造方法可以消除封装体之间的空隙，以在半导体器件的使用寿命期间最小化封装体与半导体封装的分层。 为此，可以制备电路基板，控制器和封装体。 每个封装体可以具有封装基板，粘合剂图案和封装绝缘层。 封装绝缘层可以形成在封装衬底上以包围粘合剂图案。 封装体可以形成在控制器和电路基板之间，并与控制器和电路基板接触。

公开(公告)号：US20070170575A1

公开(公告)日：2007-07-26

申请号：US11627791

申请日：2007-01-26

Applicant: Jong-Joo LEE ,  Dong-Ho LEE

Inventor： Jong-Joo LEE ,  Dong-Ho LEE

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/66 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided are a stack chip and a stack chip package having the stack chip. Internal circuits of two semiconductor chips are electrically connected to each other through an input/output buffer connected to an external connection terminal. The semiconductor chip has chip pads, input/output buffers and internal circuits connected through circuit wirings. The semiconductor chip also has connection pads connected to the circuit wirings connecting the input/output buffers to the internal circuits. The semiconductor chips include a first chip and a second chip. The connection pads of the first chip are electrically connected to the connection pads of the second chip through electrical connection means. Input signals input through the external connection terminals are input to the internal circuits of the first chip or the second chip via the chip pads and the input/output buffers of the first chip, and the connection pads of the first chip and the second chip.

Abstract translation: 提供了具有堆叠芯片的堆叠芯片和堆叠芯片封装。 两个半导体芯片的内部电路通过连接到外部连接端子的输入/输出缓冲器彼此电连接。 半导体芯片具有芯片焊盘，输入/输出缓冲器和通过电路布线连接的内部电路。 半导体芯片还具有连接到将输入/输出缓冲器连接到内部电路的电路布线的连接焊盘。 半导体芯片包括第一芯片和第二芯片。 第一芯片的连接焊盘通过电连接装置电连接到第二芯片的连接焊盘。 通过外部连接端子输入的输入信号经由芯片焊盘和第一芯片的输入/输出缓冲器以及第一芯片和第二芯片的连接焊盘输入到第一芯片或第二芯片的内部电路。