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    Method to reduce semiconductor device leakage
    71.
    发明申请
    Method to reduce semiconductor device leakage 审中-公开
    降低半导体器件泄漏的方法

    公开(公告)号：US20080135988A1

    公开(公告)日：2008-06-12

    申请号：US11636144

    申请日：2006-12-07

    申请人： Amit Subhash Kelkar ,  Joshua Li ,  Danh John C. Nguyen ,  Vijay Ullal

    发明人： Amit Subhash Kelkar ,  Joshua Li ,  Danh John C. Nguyen ,  Vijay Ullal

    IPC分类号： H01L29/30 ,  H01L21/322

    CPC分类号： H01L29/32 ,  H01L21/3225

    摘要： Various embodiments of the present invention relate to systems, devices, and methods for treating a semiconductor substrate, such as a silicon wafer, in order to reduce current leakage therein. A semiconductor substrate is provided a plurality of heating treatments that create a denuded zone adjacent to a surface of the substrate and a core zone below the denuded zone. Oxygen impurities within the denuded zone are removed through an oxygen out-diffusion heat treatment. A plurality of macroscopic bulk micro defects is generated within the core zone through the combination of an agglomeration heat treatment and a macroscopic growth heat treatment. This plurality of macroscopic bulk micro defects inhibits migration of metallic contaminants that are located within the substrate. For exemplary purposes, certain embodiments are described relating to a semiconductor wafer heated in a sequence of three treatments. Each treatment has a temperature range in which the substrate is heated and an associated time range during which the treatment occurs.

    摘要翻译： 本发明的各种实施例涉及用于处理诸如硅晶片的半导体衬底的系统，器件和方法，以便减少其中的漏电。 半导体衬底设置有多个加热处理，其产生与衬底的表面相邻的剥离区域和在剥离区域下方的芯区域。 通过氧气扩散热处理去除了裸露区域内的氧杂质。 通过附聚热处理和宏观生长热处理的组合，在芯区内产生多个宏观体微小缺陷。 这多个宏观的大块微缺陷抑制了位于衬底内的金属污染物的迁移。 为了示例的目的，描述了以三个处理的顺序加热的半导体晶片的某些实施例。 每个处理具有其中基板被加热的温度范围和处理发生的相关时间范围。

    Gettering using voids formed by surface transformation
    73.
    发明申请
    Gettering using voids formed by surface transformation 有权
    使用由表面变换形成的空隙吸收

    公开(公告)号：US20070075401A1

    公开(公告)日：2007-04-05

    申请号：US11606479

    申请日：2006-11-30

    申请人： Leonard Forbes ,  Joseph Geusic

    发明人： Leonard Forbes ,  Joseph Geusic

    IPC分类号： H01L29/30

    CPC分类号： H01L27/105 ,  H01L21/3223 ,  H01L21/324 ,  H01L27/108 ,  H01L29/78 ,  Y10S257/913

    摘要： One aspect of this disclosure relates to a memory device, comprising at least one gettering region, a memory array, a plurality of word lines and bit lines, and control circuitry. The gettering region is formed in a semiconductor substrate. The gettering region includes a precise arrangement of precisely-formed voids to getter impurities from a crystalline semiconductor region of the substrate. The memory array is formed in the crystalline semiconductor region, and includes a plurality of memory cells formed in rows and columns, and at least one transistor for each of the plurality of memory cells. Each word line is connected to a row of memory cells, and each bit line is connected to a column of memory cells. The control circuitry includes word line select circuitry and bit line select circuitry to select a number of memory cells for writing and reading operations.

    摘要翻译： 本公开的一个方面涉及一种存储器件，其包括至少一个吸杂区域，存储器阵列，多个字线和位线以及控制电路。 吸气区形成在半导体衬底中。 吸气区域包括精确设置的精确形成的空隙以从衬底的结晶半导体区域吸收杂质。 存储器阵列形成在晶体半导体区域中，并且包括以行和列形成的多个存储单元，以及用于多个存储单元中的每一个的至少一个晶体管。 每个字线连接到一行存储器单元，并且每个位线连接到一列存储单元。 控制电路包括字线选择电路和位线选择电路，以选择用于写入和读取操作的多个存储器单元。

    Apparatus with improved layers of group III-nitride semiconductor
    74.
    发明授权
    Apparatus with improved layers of group III-nitride semiconductor 有权
    具有改进的III族氮化物半导体层的装置

    公开(公告)号：US07038300B2

    公开(公告)日：2006-05-02

    申请号：US10735191

    申请日：2003-12-12

    申请人： Julia Wang-Ping Hsu ,  Michael James Manfra

    发明人： Julia Wang-Ping Hsu ,  Michael James Manfra

    IPC分类号： H01L29/30 ,  H01L31/0328

    CPC分类号： C30B29/40 ,  H01L21/02178 ,  H01L21/02241 ,  H01L21/02258 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02631 ,  H01L21/31679 ,  H01L29/2003 ,  H01L29/7371 ,  H01L29/7786 ,  H01L29/78

    摘要： An apparatus includes a crystalline substrate having a top surface, a crystalline semiconductor layer located on the top surface, and a plurality of dielectric regions. The crystalline semiconductor layer includes group III-nitride and has first and second surfaces. The first surface is in contact with the top surface. The second surface is separated from the top surface by semiconductor of the crystalline semiconductor layer. The dielectric regions are located on the second surface. Each dielectric region is distant from the other dielectric regions and covers an end of an associated lattice defect. Each lattice defect threads the crystalline semiconductor layer.

    摘要翻译： 一种装置包括具有顶表面的晶体衬底，位于顶表面上的晶体半导体层，以及多个电介质区域。 晶体半导体层包括III族氮化物并具有第一和第二表面。 第一表面与顶表面接触。 第二表面通过晶体半导体层的半导体与顶表面分离。 电介质区域位于第二表面上。 每个电介质区域远离其它电介质区域并覆盖相关晶格缺陷的一端。 每个晶格缺陷都会导致晶体半导体层。

    P-type silicon wafer and method for heat-treating the same
    75.
    发明申请
    P-type silicon wafer and method for heat-treating the same 有权
    P型硅晶片及其热处理方法

    公开(公告)号：US20060027897A1

    公开(公告)日：2006-02-09

    申请号：US11200233

    申请日：2005-08-10

    申请人： Tatsumi Kusaba ,  Hidehiko Okuda

    发明人： Tatsumi Kusaba ,  Hidehiko Okuda

    IPC分类号： H01L29/167 ,  H01L29/30

    CPC分类号： H01L21/02008 ,  H01L21/3225

    摘要： This p-type silicon wafer was subjected to heat treatment to have a resistivity of 10 Ω·cm or more, a BMD density of 5×107 defects/cm3 or more, and an n-type impurity concentration of 1×1014 atoms/cm3 or less at a depth of within 5 μm from a surface of the wafer. This method for heat-treating p-type silicon wafers, the method includes the steps of: loading p-type silicon wafers onto a wafer boat, inserting into a vertical furnace, and holding in an argon gas ambient atmosphere at a temperature of 1100 to 1300° C. for one hour; moving the wafer boat to a transfer chamber and discharging the silicon wafers; and transferring to the wafer boat silicon wafers to be heat treated next, wherein after the discharge of the heat-treated silicon wafers, the silicon wafers to be heat-treated next are transferred to the wafer boat within a waiting time of less than two hours.

    摘要翻译： 对该p型硅晶片进行热处理以具有10Ω·cm或更大的电阻率，5×10 7缺陷/ cm 3或更高的BMD密度， 并且在离晶片表面5微米深度的1×10 14原子/ cm 3或更小的n型杂质浓度。 这种用于热处理p型硅晶片的方法，该方法包括以下步骤：将p型硅晶片装载到晶片舟皿上，插入立式炉中，并在氩气环境气氛中保持在1100〜 1300℃1小时; 将晶片舟移动到转移室并排出硅晶片; 并转移到接下来要进行热处理的晶片舟状硅晶片上，其中在经过热处理的硅晶片放电之后，接下来要热处理的硅晶片在小于2小时的等待时间内转移到晶片舟皿 。

    Method of manufacturing semiconductor device
    78.
    发明授权
    Method of manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US5750443A

    公开(公告)日：1998-05-12

    申请号：US793593

    申请日：1997-03-03

    申请人： Kazuhisa Sakamoto

    发明人： Kazuhisa Sakamoto

    IPC分类号： H01L29/73 ,  H01L21/263 ,  H01L21/331 ,  H01L21/336 ,  H01L29/30 ,  H01L29/732 ,  H01L29/74 ,  H01L29/78 ,  H01L29/861 ,  H01L21/324

    CPC分类号： H01L29/66295 ,  H01L21/263 ,  Y10S148/003 ,  Y10S148/004 ,  Y10S148/08 ,  Y10S148/09 ,  Y10S148/092

    摘要： Disclosed is a method of manufacturing a semiconductor device wherein a corpuscular beam is radiated to a semiconductor substrate to create crystal defects therein. The semiconductor substrate is subjected to a heat treatment, e.g. for 1 second to 60 minutes, wherein rapid heating-up, e.g. raising temperature to 550.degree. to 850.degree. C. within 10 minutes, is done in a process prior to that of carrying out of the radiation with a corpuscular beam. By doing so, there is provided a semiconductor device which is free from degradation in electrical characteristics such as current amplification factor and has an increased switching speed, even where crystal defects are created through the radiation of corpuscular beam such as an electron beam to shorten the carrier lifetime. Thus, the inventive semiconductor device is satisfied by both requirements of switching speed and electrical characteristic.

    摘要翻译： PCT No.PCT / JP96 / 01906 371日期1997年3月3日 102（e）1997年3月3日PCT PCT 1996年7月9日PCT公布。 公开号WO97 / 03458 日期1997年1月30日公开是制造半导体器件的方法，其中将红色光束照射到半导体衬底以在其中产生晶体缺陷。 对半导体衬底进行热处理，例如， 1秒至60分钟，其中快速加热，例如， 在10分钟内将温度升至550℃至850℃，在用红细胞束进行辐射之前的过程中进行。 通过这样做，提供了一种半导体器件，其即使在通过诸如电子束的粒子束的辐射产生晶体缺陷的情况下，也不会有诸如电流放大因子等电特性的劣化，并且具有增加的切换速度，以缩短 载体寿命。 因此，本发明的半导体器件通过开关速度和电特性的要求都得到满足。