Application processor and mobile terminal

    公开(公告)号:US11860708B2

    公开(公告)日:2024-01-02

    申请号:US16982967

    申请日:2019-03-21

    发明人: Chialin Lu

    摘要: A mobile terminal and an application processor are provided. The mobile terminal includes a power management module, an application processor, a display driver chip, and a display panel. The power management module is used to output a power supply voltage to the application processor, the display driver chip, and display panel. The application processor includes a graphics processor, a graphics random access memory and a display serial interface, where the graphics random access memory is communicably connected with a codec overlay hardware of the graphic processor, and is used to receive and store an image frame outputted by the graphic processor. The graphic random access memory is communicably connected to the display serial interface to output a stored image frame to the display driver chip through a display serial interface. The display driver chip controls the display panel to display the received image frame.

    POWER SUPPLY DEVICE AND DISPLAY APPARATUS
    76.
    发明公开

    公开(公告)号:US20230400906A1

    公开(公告)日:2023-12-14

    申请号:US18303142

    申请日:2023-04-19

    申请人: Takahiro Yaoyama

    发明人: Takahiro Yaoyama

    IPC分类号: G06F1/3234

    CPC分类号: G06F1/3243

    摘要: A power supply device includes circuitry to supply power to an information processing apparatus, acquire a detection result of a person by a sensor disposed at the information processing apparatus, output a first determination result indicating whether a first condition is satisfied, and output a second determination result indicating whether a second condition is satisfied. When the detection result indicates that a person is detected in a state where the information processing apparatus is in a power saving mode, the circuitry cancels the power saving mode based on the first determination result and the second determination result. In the power saving mode, the power supplied to the information processing apparatus is reduced as compared with a normal mode. The first condition relates to an operation receivable by the information processing apparatus, and the second condition relates to a situation around the information processing apparatus.

    Fractional frequency divider and flash memory controller

    公开(公告)号:US11843379B2

    公开(公告)日:2023-12-12

    申请号:US18092908

    申请日:2023-01-03

    摘要: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

    APPARATUSES AND METHODS FOR IN-MEMORY OPERATIONS

    公开(公告)号:US20230393786A1

    公开(公告)日:2023-12-07

    申请号:US18331746

    申请日:2023-06-08

    摘要: Apparatuses and methods are provided for in-memory operations. An example apparatus includes a PIM capable device having an array of memory cells and sensing circuitry coupled to the array, where the sensing circuitry includes a sense amplifier and a compute component. The PIM capable device includes timing circuitry selectably coupled to the sensing circuitry. The timing circuitry is configured to control timing of performance of operations performed using the sensing circuitry. The PIM capable device also includes a sequencer selectably coupled to the timing circuitry. The sequencer is configured to coordinate compute operations. The apparatus also includes a source external to the PIM capable device. The sequencer is configured to receive a command instruction set from the source to initiate performance of a compute operation.