公开(公告)号：US11004805B2

公开(公告)日：2021-05-11

申请号：US16542305

申请日：2019-08-16

申请人： Winbond Electronics Corp.

发明人： Yao-Ting Tsai ,  Chiang-Hung Chen ,  Che-Fu Chuang ,  Wen Hung

IPC分类号： H01L23/00 ,  H01L21/74

摘要： Provided is a method of fabricating a semiconductor device, including the following steps. A first seal ring and a second seal ring that are separated from each other are formed on a substrate. A protective layer covering the first seal ring and the second seal ring is formed on the substrate. The protective layer between the first seal ring and the second seal ring includes a concave surface. The protective layer at the concave surface and a portion of the protective layer on the first seal ring are removed to form a spacer on a sidewall of the first seal ring, and form an opening in the protective layer. The width of the opening is greater than the width of the first seal ring, and the opening exposes a top surface of the first seal ring and the spacer.

公开(公告)号：US20210134643A1

公开(公告)日：2021-05-06

申请号：US17145338

申请日：2021-01-10

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC分类号： H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16

摘要： A 3D semiconductor device, the device including: a first level including a single crystal layer and a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors, where the interconnects between the plurality of first transistors includes forming a plurality of logic gates; a plurality of second transistors atop at least a portion of the first metal layer, where at least six of the plurality of first transistors are connected in series forming at least a portion of a NAND logic structure, where the plurality of second transistors are vertically oriented transistors, and where the plurality of second transistors are at least partially directly atop of the NAND logic structure; and a second metal layer atop at least a portion of the plurality of second transistors, where the second metal layer is aligned to the first metal layer with less than 150 nm misalignment, and where at least one of the second transistors is a junction-less transistor.

公开(公告)号：US20210074839A1

公开(公告)日：2021-03-11

申请号：US16563366

申请日：2019-09-06

申请人： Texas Instruments Incorporated

发明人： Sheldon Douglas Haynie

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/74 ,  H01L21/762 ,  H01L21/765 ,  H01L29/66

摘要： Described examples include an integrated circuit having a semiconductor substrate having an epitaxial layer located thereon, the epitaxial layer having a surface. The integrated circuit also has a buried layer formed in the semiconductor substrate, the epitaxial layer located between the buried layer and the surface. The integrated circuit also has a Schottky contact and an ohmic contact formed on the surface. The integrated circuit also has a Pdrift region in the epitaxial layer located between the ohmic contact and the Schottky contact.

公开(公告)号：US20210057271A1

公开(公告)日：2021-02-25

申请号：US16547474

申请日：2019-08-21

申请人： GLOBALFOUNDRIES INC.

发明人： Ryan W. Sporer ,  Jiehui Shu

IPC分类号： H01L21/762 ,  H01L21/74 ,  H01L21/768 ,  H01L29/06

摘要： A method forms a trench isolation opening extending into an SOI substrate, and forms an etch stop member in a portion of the insulator layer abutting a side of the trench isolation opening. The etch stop member has a higher etch selectivity than the insulator layer of the SOI substrate. A trench isolation is formed in the trench isolation opening. A contact is formed to a portion of the semiconductor layer of the SOI substrate. The etch stop member is structured to prevent contact punch through to the base substrate of the SOI substrate.

公开(公告)号：US10930652B2

公开(公告)日：2021-02-23

申请号：US16414417

申请日：2019-05-16

申请人： Micron Technology, Inc.

发明人： Shyam Surthi ,  Suraj Mathew

IPC分类号： H01L27/105 ,  H01L21/768 ,  H01L21/74 ,  H01L27/108

摘要： Methods of forming semiconductor device structures include forming trenches in an array region and in a buried digit line end region, forming a metal material in the trenches, filling the trenches with a mask material, removing the mask material in the trenches to expose a portion of the metal material, and removing the exposed portion of the metal material. A plurality of conductive contacts is formed in direct contact with the metal material in the buried digit line end region. Methods of forming a buried digit line contact include forming conductive contacts physically contacting metal material in trenches in a buried digit line end region. Vertical memory devices and apparatuses include metallic connections disposed between a buried digit line and a conductive contact in a buried digit line end region.

公开(公告)号：US20210050307A1

公开(公告)日：2021-02-18

申请号：US16542305

申请日：2019-08-16

申请人： Winbond Electronics Corp.

发明人： Yao-Ting Tsai ,  Chiang-Hung Chen ,  Che-Fu Chuang ,  Wen Hung

IPC分类号： H01L23/00 ,  H01L21/74

摘要： Provided is a method of fabricating a semiconductor device, including the following steps. A first seal ring and a second seal ring that are separated from each other are formed on a substrate. A protective layer covering the first seal ring and the second seal ring is formed on the substrate. The protective layer between the first seal ring and the second seal ring includes a concave surface. The protective layer at the concave surface and a portion of the protective layer on the first seal ring are removed to form a spacer on a sidewall of the first seal ring, and form an opening in the protective layer. The width of the opening is greater than the width of the first seal ring, and the opening exposes a top surface of the first seal ring and the spacer.

公开(公告)号：US20210043496A1

公开(公告)日：2021-02-11

申请号：US17082621

申请日：2020-10-28

申请人： Silicon Space Technologies Corporation, D.B.A. Vorago Technologies, Inc.

发明人： David R. Gifford ,  Patrice M. Parris

IPC分类号： H01L21/74 ,  H01L29/10 ,  H01L27/092 ,  H01L21/265 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/266

摘要： Structures and processes for improving radiation hardness and eliminating latch-up in integrated circuits are provided. An example process includes forming a first doped buried layer, a first well, and a second well, and using a first mask, forming a second doped buried layer only in a first region above the first doped buried layer and between at least the first well and the second well, where the first mask is configured to control spacing between the wells and the doped buried layers. The process further includes using a second mask, forming a vertical conductor located only in a second region above the first region and between at least the first well and the second well, where the vertical conductor is doped to provide a low resistance link between the second doped buried layer and at least a top surface of the substrate.

公开(公告)号：US10916468B2

公开(公告)日：2021-02-09

申请号：US15442822

申请日：2017-02-27

申请人： ELPIS TECHNOLOGIES INC.

发明人： Effendi Leobandung ,  Tenko Yamashita

IPC分类号： H01L21/74 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/535 ,  H01L29/06

摘要： Embodiments of the present invention provide methods for fabricating a semiconductor device with buried local interconnects. One method may include providing a semiconductor substrate with fins etched into the semiconductor substrate; forming a first set of spacers along the sides of the fins; depositing a tungsten film over the top surface of the substrate; etching the tungsten film to form a buried local interconnect; forming a set of gates and a second set of spacers; forming a source and drain region adjacent to the fins; depositing a first insulating material over the top surface of the substrate; and creating contact between the set of gates and the source and drain region using an upper buried local interconnect.

公开(公告)号：US10903345B2

公开(公告)日：2021-01-26

申请号：US15831112

申请日：2017-12-04

申请人： Texas Instruments Incorporated

发明人： Yufei Xiong ,  Yunlong Liu ,  Hong Yang ,  Ho Lin ,  Tianping Lv ,  Sheng Zou ,  Qiuling Jia

IPC分类号： H01L29/66 ,  H01L29/739 ,  H01L29/10 ,  H01L29/78 ,  H01L29/417 ,  H01L21/74 ,  H01L23/485 ,  H01L21/283 ,  H01L21/3213 ,  H01L29/40 ,  H01L29/06

摘要： A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.

公开(公告)号：US10861763B2

公开(公告)日：2020-12-08

申请号：US15361397

申请日：2016-11-26

申请人： Texas Instruments Incorporated

发明人： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC分类号： H01L23/34 ,  H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L23/367 ,  H01L27/02 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/768 ,  H01L23/373 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/74

摘要： An integrated circuit has a substrate which includes a semiconductor material, and an interconnect region disposed on the substrate. The integrated circuit includes a thermal routing trench in the substrate. The thermal routing trench includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal routing trench has a thermal conductivity higher than the semiconductor material contacting the thermal routing trench. The cohered nanoparticle film is formed by an additive process.