公开(公告)号：US20160204120A1

公开(公告)日：2016-07-14

申请号：US15077021

申请日：2016-03-22

Applicant: Cypress Semiconductor Corporation

Inventor： Venkatraman Prabhakar ,  Krishnaswamy Ramkumar ,  Igor Kouznetsov

IPC: H01L27/115 ,  H01L29/06

CPC classification number: H01L27/11573 ,  H01L21/28282 ,  H01L21/823462 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234

Abstract: Methods of integrating complementary SONOS devices into a CMOS process flow are described. In one embodiment, the method begins with depositing a hardmask (HM) over a substrate including a first-SONOS region and a second-SONOS region. A first tunnel mask (TUNM) is formed over the HM exposing a first portion of the HM in the second-SONOS region. The first portion of the HM is etched, a channel for a first SONOS device implanted through a first pad oxide overlying the second-SONOS region and the first TUNM removed. A second TUNM is formed exposing a second portion of the HM in the first-SONOS region. The second portion of the HM is etched, a channel for a second SONOS device implanted through a second pad oxide overlying the first-SONOS region and the second TUNM removed. The first and second pad oxides are concurrently etched, and the HM removed.

Abstract translation: 描述了将互补SONOS器件集成到CMOS工艺流程中的方法。 在一个实施例中，该方法开始于在包括第一SONOS区域和第二SONOS区域的衬底上沉积硬掩模（HM）。 在HM上形成第一隧道掩模（TUNM），暴露第二SONOS区域中的HM的第一部分。 蚀刻HM的第一部分，通过覆盖第二SONOS区域并且移除第一TUNM的第一衬垫氧化物注入第一SONOS器件的沟道。 第二TUNM被形成为暴露在第一SONOS区域中的HM的第二部分。 蚀刻HM的第二部分，通过覆盖第一SONOS区域并且移除第二TOSM的第二衬垫氧化物注入第二SONOS器件的沟道。 同时蚀刻第一和第二垫氧化物，并除去HM。

公开(公告)号：US09391178B2

公开(公告)日：2016-07-12

申请号：US13848440

申请日：2013-03-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya Fukumura

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/792 ,  H01L27/115 ,  H01L29/423 ,  G11C16/04

CPC classification number: H01L29/66833 ,  G11C16/0475 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/792

Abstract: Provided is a method of manufacturing a semiconductor device which allows an operation of the semiconductor device to be stabilized without increasing the area occupied thereby. The control gate electrode of a memory cell transistor is formed, and then the memory gate electrode thereof is formed on a lateral side of the control gate electrode. Then, memory offset spacers are formed over the side walls of the memory gate electrode. Then, the memory source region of the memory cell transistor is formed by ion implantation using the memory gate electrode, the memory offset spacers, and the like as a mask. Then, the memory drain region of the memory cell transistor is formed by ion implantation. Then, in the memory cell transistor, sidewall insulating films are formed. The memory offset spacers disappear through cleaning or the like before the sidewall insulating films are formed.

Abstract translation: 提供一种制造半导体器件的方法，其允许半导体器件的操作稳定而不增加由此占据的面积。 形成存储单元晶体管的控制栅电极，然后在控制栅电极的侧面上形成其存储栅电极。 然后，在存储栅电极的侧壁上形成记忆偏移间隔物。 然后，通过使用存储栅电极，存储器偏移间隔物等作为掩模的离子注入形成存储单元晶体管的存储源区域。 然后，通过离子注入形成存储单元晶体管的存储器漏极区域。 然后，在存储单元晶体管中形成侧壁绝缘膜。 在形成侧壁绝缘膜之前，记忆偏移间隔物通过清洁等消失。

公开(公告)号：US09391084B2

公开(公告)日：2016-07-12

申请号：US14309622

申请日：2014-06-19

Applicant: Macronix International Co., Ltd.

Inventor： Hang-Ting Lue

IPC: G11C16/04 ,  H01L27/115 ,  H01L29/792 ,  G11C16/10

CPC classification number: H01L27/11563 ,  G11C16/10 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/512 ,  H01L29/66833 ,  H01L29/792

Abstract: A memory cell includes a gate, a channel material having a channel surface and a channel valence band edge, and a dielectric stack between the gate and the channel surface. The dielectric stack comprises a multi-layer tunneling structure on the channel surface, a first charge storage nitride layer on the multi-layer tunneling structure, a first blocking oxide layer on the first charge storage nitride layer, a second charge storage nitride layer on the first blocking dielectric layer, and a second blocking oxide layer on the second charge storage nitride layer. The multi-layer tunneling structure includes a first tunneling oxide layer, a first tunneling nitride layer on the first tunneling oxide layer, and a second tunneling oxide layer on the first tunneling nitride layer.

Abstract translation: 存储单元包括栅极，具有沟道表面和沟道价带边缘的沟道材料，以及栅极和沟道表面之间的介电堆叠。 电介质堆叠包括沟道表面上的多层隧道结构，多层隧道结构上的第一电荷存储氮化物层，第一电荷存储氮化物层上的第一阻挡氧化物层，第一电荷存储氮化物层 第一阻挡介质层和第二电荷存储氮化物层上的第二阻挡氧化物层。 多层隧道结构包括第一隧道氧化物层，第一隧道氧化物层上的第一隧穿氮化物层和第一隧穿氮化物层上的第二隧穿氧化物层。

公开(公告)号：US20160190275A1

公开(公告)日：2016-06-30

申请号：US15063642

申请日：2016-03-08

Applicant: Kabushiki Kaisha Toshiba

Inventor： Daisuke MATSUSHITA ,  Yuuichiro MITANI

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/518 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3145 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.

公开(公告)号：US09373742B2

公开(公告)日：2016-06-21

申请号：US14640194

申请日：2015-03-06

Applicant: The Regents of The University of Michigan

Inventor： Xiaogan Liang ,  Hongsuk Nam ,  Sungjin Wi ,  Mikai Chen

IPC: H01L31/18 ,  H01L31/032 ,  H01L21/467 ,  B29C59/02 ,  H01L29/16

CPC classification number: H01L27/11568 ,  B29C59/02 ,  H01L21/187 ,  H01L21/3065 ,  H01L21/467 ,  H01L29/1606 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/78681 ,  H01L29/792 ,  H01L31/032 ,  H01L31/068 ,  H01L31/18 ,  H01L31/1884 ,  Y02E10/547 ,  Y02P70/521

Abstract: Plasma-assisted techniques are provided for fabricating semiconductor devices. In one aspect, a plasma is applied to a substrate before exfoliating layers of a multi-layer structure of atomically thin two-dimensional sheets onto the substrate. The exfoliated layers serve as the basis for constructing a semiconductor device. In another aspect, a p-n junction is formed by applying a plasma to top layers of a multi-layer structure of atomically thin two-dimensional sheets and then exfoliating a portion of the multi-layer structure onto a bottom electrode.

Abstract translation: 提供等离子体辅助技术来制造半导体器件。 在一个方面，在将原子薄的二维薄片的多层结构的层剥离到基底上之前，将等离子体施加到基底上。 剥离层作为构成半导体装置的基础。 在另一方面，通过将等离子体施加到原子薄的二维片的多层结构的顶层上，然后将多层结构的一部分剥离到底部电极上来形成p-n结。

公开(公告)号：US20160172296A1

公开(公告)日：2016-06-16

申请号：US14956735

申请日：2015-12-02

Applicant: Tae-Wan LIM ,  Hojong Kang ,  Joowon Park

Inventor： Tae-Wan LIM ,  Hojong Kang ,  Joowon Park

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/283 ,  H01L29/423 ,  H01L29/66 ,  H01L27/115 ,  H01L21/28 ,  H01L23/31 ,  H01L29/792

CPC classification number: H01L29/4234 ,  H01L21/28282 ,  H01L21/76805 ,  H01L21/76816 ,  H01L23/3171 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing a semiconductor device includes forming a conductive pattern on a substrate, forming a filling insulation layer covering the conductive pattern, forming a contact hole in the filling insulation layer and adjacent to the conductive pattern, forming an opening in the conductive pattern by removing a portion of the conductive pattern adjacent to the contact hole such that the opening is connected to the contact hole, and forming a contact plug filling the contact hole and the opening. A width of the opening is greater than a width of the contact hole.

Abstract translation: 一种半导体器件的制造方法，其特征在于，在基板上形成导电图案，形成覆盖所述导电图案的填充绝缘层，在所述填充绝缘层中形成与所述导电图案相邻的接触孔，在所述导体图案中形成开口， 除去与接触孔相邻的导电图案的一部分，使得开口连接到接触孔，并形成填充接触孔和开口的接触塞。 开口的宽度大于接触孔的宽度。

公开(公告)号：US20160141299A1

公开(公告)日：2016-05-19

申请号：US14548252

申请日：2014-11-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Ping HONG

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L27/11578 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/511

Abstract: A memory device is described, which includes a block of memory cells comprising a plurality of stacks of horizontal active lines such as NAND string channel lines, with a plurality of vertical slices penetrated by, and surrounding, the horizontal active lines to provide a gate-all-around structure. A memory film is disposed between the horizontal active lines in the plurality of stacks and the vertical slices in the plurality of vertical slices. A 3D, horizontal channel, gate-all-around NAND flash memory is provided. A method for manufacturing a memory involves a buttress process. The buttress process enables horizontal channel, gate-all-around structures.

Abstract translation: 描述了一种存储器件，其包括一组存储器单元，该存储器单元包括多个水平有源线的堆叠，例如NAND串通道线，多个垂直切片穿过并围绕水平有源线，以提供栅极 - 全方位的结构。 存储膜设置在多个堆叠中的水平有源线和多个垂直片中的垂直片之间。 提供了3D，水平通道，全栅NAND闪存。 存储器的制造方法包括支撑工艺。 支撑过程支持水平通道，闸门全能结构。

公开(公告)号：US09337048B2

公开(公告)日：2016-05-10

申请号：US14493608

申请日：2014-09-23

Applicant: Macronix International Co., Ltd.

Inventor： Ching-Hsiung Lee ,  Shih-Chang Tsai

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/792

Abstract: A method of fabricating wordlines in semiconductor memory structures is disclosed that eliminates stringers between wordlines while maintaining a stable distribution of threshold voltage. A liner is deposited before performing a wordline etch, and a partial wordline etch is then performed. Remaining portions of the liner are removed, and the wordline etch is completed to form gates having vertical or tapered profiles.

Abstract translation: 公开了一种在半导体存储器结构中制造字线的方法，其消除了字线之间的桁条，同时保持了阈值电压的稳定分布。 在执行字线蚀刻之前沉积衬垫，然后执行部分字线蚀刻。 衬里的剩余部分被去除，并且字线蚀刻完成以形成具有垂直或锥形轮廓的门。

公开(公告)号：US20160126328A1

公开(公告)日：2016-05-05

申请号：US14540588

申请日：2014-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang-soo SEOL

IPC: H01L29/423 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L29/42344 ,  H01L27/1157 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/792

Abstract: Memory devices are provided, the memory devices include a tunneling insulating layer disposed on a substrate, a charge storage layer disposed on the tunneling insulating layer, a blocking insulating layer disposed on the charge storage layer and a control gate electrode disposed on the blocking insulating layer. The control gate electrode may have an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode to concentrate charge density distribution on a central portion of a memory cell.

Abstract translation: 提供存储器件，存储器件包括设置在衬底上的隧道绝缘层，设置在隧道绝缘层上的电荷存储层，设置在电荷存储层上的阻挡绝缘层和设置在阻挡绝缘层上的控制栅电极 。 与控制栅极的中心部分相比，控制栅电极可以具有与阻挡绝缘层相距更远的边缘部分，以将电荷密度分布集中在存储器单元的中心部分上。

公开(公告)号：US20160118394A1

公开(公告)日：2016-04-28

申请号：US14989999

申请日：2016-01-07

Applicant: Renesas Electronics Corporation

Inventor： Koichi TOBA ,  Hiraku CHAKIHARA ,  Yoshiyuki KAWASHIMA ,  Kentaro SAITO ,  Takashi HASHIMOTO

IPC: H01L27/115 ,  H01L27/092 ,  H01L21/8234

CPC classification number: H01L29/7847 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

Abstract: To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

Abstract translation: 改善具有非易失性存储器的半导体器件。 形成第一MISFET，第二MISFET和存储单元，并在其上形成由氧化硅膜制成的阻挡膜。 然后，在阻挡膜上形成由氮化硅膜构成的应力施加膜，除去第二MISFET和存储单元上的应力施加膜。 此后，进行热处理以向第一MISFET施加应力。 因此，SMT不应用于每个元件，而是被选择性地应用。 这可以降低由于形成应力施加膜的氮化硅膜中的H（氢）导致的第二MISFET的劣化程度。 这也可以由于形成应力施加膜的氮化硅膜中的H（氢）而降低存储单元的特性的劣化程度。