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公开(公告)号：US20160172296A1
公开(公告)日：2016-06-16
申请号：US14956735
申请日：2015-12-02
Applicant: Tae-Wan LIM , Hojong Kang , Joowon Park
Inventor： Tae-Wan LIM , Hojong Kang , Joowon Park
IPC: H01L23/528 , H01L21/768 , H01L21/283 , H01L29/423 , H01L29/66 , H01L27/115 , H01L21/28 , H01L23/31 , H01L29/792
CPC classification number: H01L29/4234 , H01L21/28282 , H01L21/76805 , H01L21/76816 , H01L23/3171 , H01L23/485 , H01L23/5226 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L29/66833 , H01L29/7926 , H01L2924/0002 , H01L2924/00
Abstract: A method for manufacturing a semiconductor device includes forming a conductive pattern on a substrate, forming a filling insulation layer covering the conductive pattern, forming a contact hole in the filling insulation layer and adjacent to the conductive pattern, forming an opening in the conductive pattern by removing a portion of the conductive pattern adjacent to the contact hole such that the opening is connected to the contact hole, and forming a contact plug filling the contact hole and the opening. A width of the opening is greater than a width of the contact hole.
Abstract translation: 一种半导体器件的制造方法，其特征在于，在基板上形成导电图案，形成覆盖所述导电图案的填充绝缘层，在所述填充绝缘层中形成与所述导电图案相邻的接触孔，在所述导体图案中形成开口， 除去与接触孔相邻的导电图案的一部分，使得开口连接到接触孔，并形成填充接触孔和开口的接触塞。 开口的宽度大于接触孔的宽度。
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公开(公告)号：US20170271463A1
公开(公告)日：2017-09-21
申请号：US15591736
申请日：2017-05-10
Applicant: Tae-Wan LIM , Hojong KANG , Joowon PARK
Inventor： Tae-Wan LIM , Hojong KANG , Joowon PARK
IPC: H01L29/423 , H01L29/792 , H01L23/31 , H01L27/11582 , H01L21/28 , H01L23/485 , H01L23/522 , H01L29/66 , H01L27/1157 , H01L27/11575 , H01L21/768
CPC classification number: H01L29/4234 , H01L21/28282 , H01L21/76805 , H01L21/76816 , H01L23/3171 , H01L23/485 , H01L23/5226 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L29/66833 , H01L29/7926 , H01L2924/0002 , H01L2924/00
Abstract: A method for manufacturing a semiconductor device includes forming a conductive pattern on a substrate, forming a filling insulation layer covering the conductive pattern, forming a contact hole in the filling insulation layer and adjacent to the conductive pattern, forming an opening in the conductive pattern by removing a portion of the conductive pattern adjacent to the contact hole such that the opening is connected to the contact hole, and forming a contact plug filling the contact hole and the opening. A width of the opening is greater than a width of the contact hole.
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公开(公告)号：US10103236B2
公开(公告)日：2018-10-16
申请号：US15591736
申请日：2017-05-10
Applicant: Tae-Wan Lim , Hojong Kang , Joowon Park
Inventor： Tae-Wan Lim , Hojong Kang , Joowon Park
IPC: H01L23/52 , H01L21/4763 , H01L29/423 , H01L23/485 , H01L29/792 , H01L23/31 , H01L27/11582 , H01L21/28 , H01L21/768 , H01L23/522 , H01L29/66 , H01L27/1157 , H01L27/11575
Abstract: A method for manufacturing a semiconductor device includes forming a conductive pattern on a substrate, forming a filling insulation layer covering the conductive pattern, forming a contact hole in the filling insulation layer and adjacent to the conductive pattern, forming an opening in the conductive pattern by removing a portion of the conductive pattern adjacent to the contact hole such that the opening is connected to the contact hole, and forming a contact plug filling the contact hole and the opening. A width of the opening is greater than a width of the contact hole.
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公开(公告)号：US20160293626A1
公开(公告)日：2016-10-06
申请号：US15059993
申请日：2016-03-03
Applicant: JONGWON KIM , HYEONG PARK , HYUNMIN LEE , HOJONG KANG , JOOWON PARK , SEUNGMIN SONG
Inventor： JONGWON KIM , HYEONG PARK , HYUNMIN LEE , HOJONG KANG , JOOWON PARK , SEUNGMIN SONG
IPC: H01L27/115 , H01L23/528 , H01L23/522
CPC classification number: H01L27/11582 , H01L27/11565 , H01L27/11575
Abstract: A semiconductor memory device includes a stack structure including gate electrodes vertically stacked on a substrate and a vertical channel part penetrating the gate electrodes, a bit line connected to the vertical channel part, and a plurality of conductive lines connected to the gate electrodes on the stack structure. The conductive lines form a plurality of stacked layers and include first conductive lines and second conductive lines. The number of the first conductive lines disposed at a first level from the substrate is different from the number of the second conductive lines disposed at a second level from the substrate. The first level is different from the second level.
Abstract translation: 半导体存储器件包括堆叠结构，其包括垂直堆叠在衬底上的栅电极和穿过栅电极的垂直沟道部分，连接到垂直沟道部分的位线和连接到堆叠上的栅电极的多条导线 结构体。 导线形成多个堆叠层，并且包括第一导线和第二导线。 从衬底设置在第一电平的第一导电线的数量不同于从衬底设置在第二电平的第二导电线的数量。 第一级与第二级不同。
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公开(公告)号：US09711603B2
公开(公告)日：2017-07-18
申请号：US14956735
申请日：2015-12-02
Applicant: Tae-Wan Lim , Hojong Kang , Joowon Park
Inventor： Tae-Wan Lim , Hojong Kang , Joowon Park
IPC: H01L23/52 , H01L21/4763 , H01L29/423 , H01L23/31 , H01L27/11582 , H01L21/28 , H01L23/485 , H01L23/522 , H01L27/1157 , H01L27/11575 , H01L21/768 , H01L29/66 , H01L29/792
CPC classification number: H01L29/4234 , H01L21/28282 , H01L21/76805 , H01L21/76816 , H01L23/3171 , H01L23/485 , H01L23/5226 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L29/66833 , H01L29/7926 , H01L2924/0002 , H01L2924/00
Abstract: A method for manufacturing a semiconductor device includes forming a conductive pattern on a substrate, forming a filling insulation layer covering the conductive pattern, forming a contact hole in the filling insulation layer and adjacent to the conductive pattern, forming an opening in the conductive pattern by removing a portion of the conductive pattern adjacent to the contact hole such that the opening is connected to the contact hole, and forming a contact plug filling the contact hole and the opening. A width of the opening is greater than a width of the contact hole.
