公开(公告)号：US20140077308A1

公开(公告)日：2014-03-20

申请号：US14086563

申请日：2013-11-21

申请人： GLOBAL FOUNDRIES Inc.

发明人： Peter Baars ,  Richard Carter ,  Andy Wei

IPC分类号： H01L27/092 ,  H01L23/28

CPC分类号： H01L27/092 ,  H01L21/28512 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/28 ,  H01L23/485 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7847 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a plurality of NMOS transistor elements, each including a first gate electrode structure above a first active region, at least two of the plurality of first gate electrode structures including a first encapsulating stack having a first dielectric cap layer and a first sidewall spacer stack. The semiconductor device also includes a plurality of PMOS transistor elements, each including a second gate electrode structure above a second active region, wherein at least two of the plurality of second gate electrode structures include a second encapsulating stack having a second dielectric cap layer and a second sidewall spacer stack. Additionally, the first and second sidewall spacer stacks each include at least three dielectric material layers, wherein each of the three dielectric material layers of the first and second sidewall spacer stacks include the same dielectric material.

摘要翻译： 半导体器件包括多个NMOS晶体管元件，每个NMOS晶体管元件均包括在第一有源区上方的第一栅极电极结构，多个第一栅电极结构中的至少两个包括第一封装堆叠，第一封装堆叠具有第一电介质盖层和第一侧壁 间隔堆叠 半导体器件还包括多个PMOS晶体管元件，每个PMOS晶体管元件包括在第二有源区上方的第二栅极电极结构，其中多个第二栅电极结构中的至少两个包括具有第二电介质盖层和 第二侧壁间隔堆叠。 另外，第一和第二侧壁间隔堆叠每个包括至少三个介电材料层，其中第一和第二侧壁间隔物叠层的三个介电材料层中的每一个包括相同的电介质材料。

公开(公告)号：US08610281B1

公开(公告)日：2013-12-17

申请号：US13633234

申请日：2012-10-02

申请人： GLOBALFOUNDRIES Inc.

发明人： Andy T. Nguyen ,  Kuldeep Amarnath ,  Ravi P. Gutala

IPC分类号： H01L23/52

CPC分类号： H01L23/481 ,  H01L23/5223 ,  H01L25/0657 ,  H01L27/0694 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and structures for a double-sided semiconductor structure using through-silicon vias (TSVs) are disclosed. The double-sided structure has functional circuits on both the front and back sides, interconnected by one or more TSVs. In some embodiments, multiple double-sided structures are combined to create 3D semiconductor structures with increased circuit density.

摘要翻译： 公开了使用硅通孔（TSV）的双面半导体结构的方法和结构。 双面结构在前后两侧具有功能电路，由一个或多个TSV互连。 在一些实施例中，组合多个双面结构以产生具有增加的电路密度的3D半导体结构。

公开(公告)号：US20130062726A1

公开(公告)日：2013-03-14

申请号：US13231194

申请日：2011-09-13

申请人： Andreas Kurz ,  Maciej Wiatr

发明人： Andreas Kurz ,  Maciej Wiatr

IPC分类号： H01L29/86 ,  H01L21/265

CPC分类号： H01L23/5256 ,  H01L21/26506 ,  H01L2924/0002 ,  H01L2924/00

摘要： Post programming resistance of a semiconductor fuse is enhanced by using an implantation to form an amorphous silicon layer and to break up an underlying high-κ/metal gate. Embodiments include forming a shallow trench isolation (STI) region in a silicon substrate, forming a high-κ dielectric layer on the STI region, forming a metal gate on the high-κ dielectric layer, forming a polysilicon layer over the metal gate, performing an implantation to convert the polysilicon layer into an amorphous silicon layer, wherein the implantation breaks up the metal gate, and forming a silicide on the amorphous silicon layer. By breaking up the metal gate, electrical connection of the fuse contacts through the metal gate is eliminated.

公开(公告)号：US08241927B2

公开(公告)日：2012-08-14

申请号：US12579216

申请日：2009-10-14

申请人： Jihong Choi ,  Yongsik Moon ,  Roderick Augur ,  Eden Zielinski

发明人： Jihong Choi ,  Yongsik Moon ,  Roderick Augur ,  Eden Zielinski

IPC分类号： H01L21/66

CPC分类号： H01L22/34 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are provided that relate to the capacitive monitoring of characteristic pertaining to layer formed during the back end-of-the-line (BEOL) processing of a semiconductor device. In one embodiment, a method includes the steps of forming a first capacitor array including first and second overlying contacts each formed in a different one of the plurality of BEOL layers, measuring the interlayer capacitance between the first and second overlying contacts, and converting the measured interlayer capacitance to a distance between the first and second overlying contacts.

摘要翻译： 提供了涉及在半导体器件的后端（BEOL）处理期间形成的层的特性的电容性监测的方法。 在一个实施例中，一种方法包括以下步骤：形成第一电容器阵列，该第一电容器阵列包括第一和第二上覆触点，每个形成在多个BEOL层中的不同的一个中，测量第一和第二覆盖触点之间的层间电容， 层间电容与第一和第二上覆触点之间的距离。

公开(公告)号：US07790624B2

公开(公告)日：2010-09-07

申请号：US12174497

申请日：2008-07-16

申请人： Balgovind Sharma

发明人： Balgovind Sharma

IPC分类号： H01L21/302 ,  H01L21/44

CPC分类号： H01L21/32134 ,  H01L21/823842

摘要： Methods for removing metal-comprising materials from semiconductor materials are provided. In accordance with an exemplary embodiment, a method comprises providing a metal-comprising material overlying a semiconductor material and exposing the metal-comprising material to an aqueous non-chlorine-comprising acid solution having a pH of about less 7.

摘要翻译： 提供了从半导体材料中除去含金属材料的方法。 根据示例性实施例，一种方法包括提供覆盖半导体材料的金属包覆材料，并将含金属的材料暴露于pH约为7以下的含水非氯化酸溶液。

公开(公告)号：US10278306B2

公开(公告)日：2019-04-30

申请号：US14632194

申请日：2015-02-26

申请人： GLOBALFOUNDRIES INC.

发明人： Thomas J. Brunschwiler ,  Urs Kloter ,  Ryan Joseph Linderman ,  Bruno Michel ,  Hugo E. Rothuizen ,  Reto Waelchli

IPC分类号： F28D1/04 ,  H05K7/20 ,  H01L23/427 ,  H01L23/473 ,  H01L23/34 ,  G06F1/20

摘要： The invention relates to a cooling arrangement comprising a heat spreader (2) comprising a first surface (5), a second surface (8), at least one heat absorption chamber (9) and at least one heat dissipation chamber (10), the at least one heat absorption chamber (9) being in thermal contact with the first surface (5) and the at least one heat dissipation chamber (10) being in thermal contact with the second surface (8) and hydraulically coupled to the at least one heat absorption chamber (9). A cooling fluid (13) can be driven from the heat absorption chamber (9) to the heat dissipation chamber (10) using a plurality of flow patterns for cooling the first surface (5).

公开(公告)号：US10096587B1

公开(公告)日：2018-10-09

申请号：US15794688

申请日：2017-10-26

申请人： GLOBALFOUNDRIES Inc.

发明人： Mickey Yu ,  Alain Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  You Li ,  Robert J. Gauthier, Jr.

IPC分类号： H01L27/02 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/535 ,  H01L29/06

摘要： Diode structures and methods of fabricating diode structures. First and second gate structures are formed with the second gate structure arranged parallel to the first gate structure. First and second fins are formed that extend vertically from a top surface of a substrate. The first and second fins are arranged between the first gate structure and the second gate structure. A contact structure is coupled with the first fin and the second fin. The contact structure is laterally arranged between the first gate structure and the second gate structure.

公开(公告)号：US09722057B2

公开(公告)日：2017-08-01

申请号：US14747668

申请日：2015-06-23

申请人： GLOBALFOUNDRIES INC.

发明人： Renata Camillo-Castillo ,  Vibhor Jain ,  Marwan H. Khater

IPC分类号： H01L29/737 ,  H01L21/265 ,  H01L21/762 ,  H01L21/764 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

CPC分类号： H01L29/7371 ,  H01L21/26586 ,  H01L21/76237 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732

摘要： Device structure and fabrication methods for a bipolar junction transistor. A trench isolation region is formed that bounds an active device region along a sidewall. A dielectric region is formed that extends laterally from the sidewall of the active device region into the active device region. The dielectric region is located beneath a top surface of the active device region such that a section of the active device region is located between the top surface and the dielectric region.

公开(公告)号：US09666717B2

公开(公告)日：2017-05-30

申请号：US14217691

申请日：2014-03-18

申请人： GLOBALFOUNDRIES Inc.

发明人： Jagar Singh ,  Konstantin G. Korablev ,  Andy Chih-Hung Wei

IPC分类号： H01L29/40 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/36 ,  H01L21/265

CPC分类号： H01L29/7851 ,  H01L21/26586 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/36 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795

摘要： Approaches for altering the threshold voltage (e.g., to zero threshold voltage) in a fin-type field effect transistor (FinFET) device are provided. In embodiments of the invention, a first N+ region and a second N+ region are formed on a finned substrate that has a p-well construction. A region of the finned substrate located between the first N+ region and the second N+ region is doped with a negative implant species to form an n-well. The size and/or composition of this n-well region can be adjusted in view of the existing p-well construction of the substrate device to change the threshold voltage of the FinFET device (e.g., to yield a zero threshold voltage FinFET device).

公开(公告)号：US09496133B1

公开(公告)日：2016-11-15

申请号：US15161258

申请日：2016-05-22

申请人： International Business Machines Corporation ,  GlobalFoundries, Inc.

发明人： Balasubramanian Pranatharthiharan ,  Hui Zang

IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L27/11 ,  H01L21/3105

CPC分类号： H01L27/1104 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/26506 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1116 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： A method for preventing epitaxial growth in a semiconductor device is described. The method cuts the fins of a FinFET structure to form a set of exposed fin ends. A plasma nitridation process is performed to the set of exposed fin ends. The plasma nitridation process forms a set of nitride layer covered fin ends. Dielectric material is deposited over the FinFET structure. The dielectric is etched to reveal sidewalls of the fins and the set of nitride layer covered fin ends. The nitride layer prevents epitaxial growth at the set of spacer covered fin ends.

摘要翻译： 描述了一种用于防止半导体器件中的外延生长的方法。 该方法切割FinFET结构的翅片以形成一组暴露的翅片末端。 对一组暴露的翅片端进行等离子体氮化处理。 等离子体氮化处理形成一组覆盖鳍片的氮化物层。 电介质材料沉积在FinFET结构上。 电介质被蚀刻以显示翅片的侧壁和一组氮化物层覆盖的翅片端部。 氮化物层防止在间隔件覆盖的翅片端部处的外延生长。