公开(公告)号：US20230364733A1

公开(公告)日：2023-11-16

申请号：US18359396

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Hsun Chang ,  Hung Yen ,  Chi-Hsiang Shen ,  Fu-Ming Huang ,  Chun-Chieh Lin ,  Tsung Hsien Chang ,  Ji Cui ,  Liang-Guang Chen ,  Chih Hung Chen ,  Kei-Wei Chen

IPC: B24B37/16 ,  B24B57/02 ,  B24B37/015 ,  H01L21/306

CPC classification number: B24B37/16 ,  B24B57/02 ,  B24B37/015 ,  H01L21/30625

Abstract: A chemical mechanical planarization apparatus includes a multi-zone platen comprising a plurality of individually controlled concentric toroids. The rotation direction, rotation speed, applied force, relative height, and temperature of each concentric toroid is individually controlled. Concentric polishing pads are affixed to an upper surface of each of the individually controlled concentric toroids. The chemical mechanical planarization apparatus includes a single central slurry source or includes individual slurry sources for each individually controlled concentric toroid.

公开(公告)号：US20230321789A1

公开(公告)日：2023-10-12

申请号：US18334526

申请日：2023-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Kai Chen ,  Shang-Yu Wang ,  Wan-Chun Pan ,  Zink Wei ,  Hui-Chi Huang ,  Kei-Wei Chen

IPC: B24B49/12 ,  G01N21/64 ,  B24B53/017 ,  B24B37/20 ,  B24B37/12

CPC classification number: B24B49/12 ,  G01N21/6456 ,  B24B53/017 ,  B24B37/20 ,  B24B37/12

Abstract: A method of operating a chemical mechanical planarization (CMP) tool includes attaching a polishing pad to a first surface of a platen of the CMP tool using a glue; removing the polishing pad from the platen, wherein after removing the polishing pad, residue portions of the glue remain on the first surface of the platen; identifying locations of the residue portions of the glue on the first surface of the platen using a fluorescent material; and removing the residue portions of the glue from the first surface of the platen.

公开(公告)号：US20230271298A1

公开(公告)日：2023-08-31

申请号：US18312753

申请日：2023-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Michael Yen ,  Kao-Feng Liao ,  Hsin-Ying Ho ,  Chun-Wen Hsiao ,  Sheng-Chao Chuang ,  Ting-Hsun Chang ,  Fu-Ming Huang ,  Chun-Chieh Lin ,  Peng-Chung Jangjian ,  Ji James Cui ,  Liang-Guang Chen ,  Chih Hung Chen ,  Kei-Wei Chen

IPC: B24B37/26 ,  B24B37/005 ,  B24B37/24 ,  B24B37/04

CPC classification number: B24B37/26 ,  B24B37/005 ,  B24B37/24 ,  B24B37/042

Abstract: A chemical mechanical planarization (CMP) tool includes a platen and a polishing pad attached to the platen, where a first surface of the polishing pad facing away from the platen includes a first polishing zone and a second polishing zone, where the first polishing zone is a circular region at a center of the first surface of the polishing pad, and the second polishing zone is an annular region around the first polishing zone, where the first polishing zone and the second polishing zone have different surface properties.

公开(公告)号：US11710659B2

公开(公告)日：2023-07-25

申请号：US17646024

申请日：2021-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Chieh Wu ,  Tang-Kuei Chang ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ting-Kui Chang ,  Chia Hsuan Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H01L23/485 ,  H01L21/3115 ,  H01L23/532

CPC classification number: H01L21/76883 ,  H01L21/76825 ,  H01L23/5226 ,  H01L21/31155 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/485 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

公开(公告)号：US11633829B2

公开(公告)日：2023-04-25

申请号：US16573957

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Sheng Lin ,  Chi-Hsiang Shen ,  Chi-Jen Liu ,  Chun-Wei Hsu ,  Yang-Chun Cheng ,  Kei-Wei Chen

IPC: B24B37/015 ,  B24B37/20 ,  B24B53/017 ,  B24B57/02 ,  B24B49/14

Abstract: A chemical mechanical polishing (CMP) system includes a polishing pad configured to polish a substrate. The CMP system further includes a heating system configured to adjust a temperature of the polishing pad. The heating system comprises at least one heating element spaced apart from the polishing pad. The CMP system further includes a sensor configured to measure the temperature of the polishing pad.

公开(公告)号：US20230118617A1

公开(公告)日：2023-04-20

申请号：US18066934

申请日：2022-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Kung ,  Hui-Chi Huang ,  Kei-Wei Chen ,  Yen-Ting Chen

IPC: H01L21/306 ,  B24B37/24 ,  H01L21/321

Abstract: Provided herein are polishing pads in which microcapsules that include a polymer material and are dispersed, as well as methods of making and using the same. Such microcapsules are configured to break open (e.g., when the polishing pad is damaged during the dressing process), which releases the polymer material. When contacted with ultraviolet light the polymer material at least partially cures, healing the damage to the polishing pad. Such polishing pads have a longer lifetime and a more stable remove rate when compared to standard polishing pads.

公开(公告)号：US11631618B2

公开(公告)日：2023-04-18

申请号：US17143032

申请日：2021-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih Hung Chen ,  Kei-Wei Chen ,  Ying-Lang Wang

IPC: H01L21/66 ,  H01L21/321 ,  B24B37/013 ,  G01B7/06

Abstract: Various embodiments provide a thickness sensor and method for measuring a thickness of discrete conductive features, such as conductive lines and plugs. In one embodiment, the thickness sensor generates an Eddy current in a plurality of discrete conductive features, and measures the generated Eddy current generated in the discrete conductive features. The thickness sensor has a small sensor spot size, and amplifies peaks and valleys of the measured Eddy current. The thickness sensor determines a thickness of the discrete conductive features based on a difference between a minimum amplitude value and a maximum amplitude value of the measured Eddy current.

公开(公告)号：US11594680B2

公开(公告)日：2023-02-28

申请号：US17463790

申请日：2021-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Miao Liu ,  Bwo-Ning Chen ,  Kei-Wei Chen

IPC: H01L45/00

Abstract: A method of forming a semiconductor device includes patterning a mask layer and a semiconductor material to form a first fin and a second fin with a trench interposing the first fin and the second fin. A first liner layer is formed over the first fin, the second fin, and the trench. An insulation material is formed over the first liner layer. A first anneal is performed, followed by a first planarization of the insulation material to form a first planarized insulation material. After which, a top surface of the first planarized insulation material is over a top surface of the mask layer. A second anneal is performed, followed by a second planarization of the first planarized insulation material to form a second planarized insulation material. The insulation material is etched to form shallow trench isolation (STI) regions, and a gate structure is formed over the semiconductor material.

公开(公告)号：US20220367257A1

公开(公告)日：2022-11-17

申请号：US17869560

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Kung ,  Chih-Chieh Chang ,  Kao-Feng Liao ,  Hui-Chi Huang ,  Kei-Wei Chen

IPC: H01L21/768

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.

公开(公告)号：US20220262951A1

公开(公告)日：2022-08-18

申请号：US17734687

申请日：2022-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsiung Tsai ,  Kuo-Feng Yu ,  Kei-Wei Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/223 ,  H01L21/324 ,  H01L21/225 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/3115

Abstract: A semiconductor structure includes a substrate, a first semiconductor fin, a second semiconductor fin, and a first lightly-doped drain (LDD) region. The first semiconductor fin is disposed on the substrate. The first semiconductor fin has a top surface and sidewalls. The second semiconductor fin is disposed on the substrate. The first semiconductor fin and the second semiconductor fin are separated from each other at a nanoscale distance. The first lightly-doped drain (LDD) region is disposed at least in the top surface and the sidewalls of the first semiconductor fin.