公开(公告)号：US11679469B2

公开(公告)日：2023-06-20

申请号：US16550021

申请日：2019-08-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Michael Yen ,  Kao-Feng Liao ,  Hsin-Ying Ho ,  Chun-Wen Hsiao ,  Sheng-Chao Chuang ,  Ting-Hsun Chang ,  Fu-Ming Huang ,  Chun-Chieh Lin ,  Peng-Chung Jangjian ,  Ji James Cui ,  Liang-Guang Chen ,  Chih Hung Chen ,  Kei-Wei Chen

IPC: B24B37/26 ,  B24B37/005 ,  B24B37/24 ,  B24B37/04

CPC classification number: B24B37/26 ,  B24B37/005 ,  B24B37/042 ,  B24B37/24

Abstract: A chemical mechanical planarization (CMP) tool includes a platen and a polishing pad attached to the platen, where a first surface of the polishing pad facing away from the platen includes a first polishing zone and a second polishing zone, where the first polishing zone is a circular region at a center of the first surface of the polishing pad, and the second polishing zone is an annular region around the first polishing zone, where the first polishing zone and the second polishing zone have different surface properties.

公开(公告)号：US11437497B2

公开(公告)日：2022-09-06

申请号：US16376293

申请日：2019-04-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ji-Yin Tsai ,  Jung-Jen Chen ,  Pei-Ren Jeng ,  Chii-Horng Li ,  Kei-Wei Chen ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L29/161 ,  H01L21/223 ,  H01L29/78 ,  H01L21/306 ,  H01L21/02

Abstract: In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.

公开(公告)号：US11373879B2

公开(公告)日：2022-06-28

申请号：US17019234

申请日：2020-09-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Tung-Kai Chen ,  Ching-Hsiang Tsai ,  Kao-Feng Liao ,  Chih-Chieh Chang ,  Chun-Hao Kung ,  Fang-I Chih ,  Hsin-Ying Ho ,  Chia-Jung Hsu ,  Hui-Chi Huang ,  Kei-Wei Chen

IPC: H01L21/321 ,  H01L21/3105 ,  H01L21/28

Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.

公开(公告)号：US11355635B2

公开(公告)日：2022-06-07

申请号：US16741364

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Hsiung Tsai ,  Kuo-Feng Yu ,  Kei-Wei Chen

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/223 ,  H01L21/324 ,  H01L21/225 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/3115

Abstract: A semiconductor structure includes a substrate, a first semiconductor fin, a second semiconductor fin, and a first lightly-doped drain (LDD) region. The first semiconductor fin is disposed on the substrate. The first semiconductor fin has a top surface and sidewalls. The second semiconductor fin is disposed on the substrate. The first semiconductor fin and the second semiconductor fin are separated from each other at a nanoscale distance. The first lightly-doped drain (LDD) region is disposed at least in the top surface and the sidewalls of the first semiconductor fin.

公开(公告)号：US20210391208A1

公开(公告)日：2021-12-16

申请号：US16902203

申请日：2020-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ji Cui ,  Fu-Ming Huang ,  Ting-Kui Chang ,  Tang-Kuei Chang ,  Chun-Chieh Lin ,  Wei-Wei Liang ,  Chi-Hsiang Shen ,  Ting-Hsun Chang ,  Li-Chieh Wu ,  Hung Yen ,  Chi-Jen Liu ,  Liang-Guang Chen ,  Kei-Wei Chen

IPC: H01L21/768 ,  C09G1/02 ,  C09K3/14

Abstract: A method for CMP includes following operations. A metal layer is received. A CMP slurry composition is provided in a CMP apparatus. The CMP slurry composition includes at least a first oxidizer and a second oxidizer different from each other. The first oxidizer is oxidized to form a peroxidant by the second oxidizer. A portion of the metal layer is oxidized to form a first metal oxide by the peroxidant. The first metal oxide is re-oxidized to form a second metal oxide by the second oxidizer.

公开(公告)号：US10937691B2

公开(公告)日：2021-03-02

申请号：US16559336

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia Hsuan Lee ,  Chun-Wei Hsu ,  Chia-Wei Ho ,  Chi-Hsiang Shen ,  Li-Chieh Wu ,  Jian-Ci Lin ,  Chi-Jen Liu ,  Yi-Sheng Lin ,  Yang-Chun Cheng ,  Liang-Guang Chen ,  Kuo-Hsiu Wei ,  Kei-Wei Chen

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/3105 ,  C09G1/02

Abstract: Methods of forming a slurry and methods of performing a chemical mechanical polishing (CMP) process utilized in manufacturing semiconductor devices, as described herein, may be performed on semiconductor devices including integrated contact structures with ruthenium (Ru) plug contacts down to a semiconductor substrate. The slurry may be formed by mixing a first abrasive, a second abrasive, and a reactant with a solvent. The first abrasive may include a first particulate including titanium dioxide (TiO2) particles and the second abrasive may include a second particulate that is different from the first particulate. The slurry may be used in a CMP process for removing ruthenium (Ru) materials and dielectric materials from a surface of a workpiece resulting in better WiD loading and planarization of the surface for a flat profile.

公开(公告)号：US10749008B2

公开(公告)日：2020-08-18

申请号：US16051002

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Hsiung Tsai ,  Kuo-Feng Yu ,  Chien-Tai Chan ,  Ziwei Fang ,  Kei-Wei Chen ,  Huai-Tei Yang

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L21/225

Abstract: A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack.

公开(公告)号：US20200101582A1

公开(公告)日：2020-04-02

申请号：US16252183

申请日：2019-01-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Wen Liu ,  Hao-Yun Cheng ,  Che-Hao Tu ,  Kei-Wei Chen

IPC: B24B57/02 ,  B24B37/10 ,  B24B37/30 ,  B24B37/04 ,  H01L21/306

Abstract: A system controls a flow of a chemical mechanical polish (CMP) slurry into a chamber to form a slurry reservoir within the chamber. Once the slurry reservoir has been formed within the chamber, the system moves a polishing head to position and force a surface of a wafer that is attached to the polishing head into contact with a polishing pad attached to a platen within the chamber. A wafer/pad interface is formed at the surface of the wafer forced into contact with the polishing pad and the wafer/pad interface is disposed below an upper surface of the slurry reservoir. During CMP processing, the system controls one or more of a level, a force, and a rotation of the platen, a position, a force and a rotation of the polishing head to conduct the CMP processing of the surface of the wafer at the wafer/pad interface.

公开(公告)号：US20200043786A1

公开(公告)日：2020-02-06

申请号：US16450665

申请日：2019-06-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Chieh Wu ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Tang-Kuei Chang ,  Chia Hsuan Lee ,  Jian-Ci Lin

IPC: H01L21/768 ,  H01L21/321 ,  H01L23/532 ,  H01L23/535 ,  C09G1/04

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a conductive feature over a semiconductor substrate and forming a dielectric layer over the conductive feature. The method also includes forming an opening in the dielectric layer to expose the conductive feature. The method further includes forming a conductive material to overfill the opening. In addition, the method includes thinning the conductive material using a chemical mechanical polishing process. A slurry used in the chemical mechanical polishing process includes an iron-containing oxidizer that oxidizes a portion of the conductive material.

公开(公告)号：US20200043745A1

公开(公告)日：2020-02-06

申请号：US16179307

申请日：2018-11-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Hao Kung ,  Tung-Kai Chen ,  Chih-Chieh Chang ,  Kao-Feng Liao ,  Hui-Chi Huang ,  Kei-Wei Chen

IPC: H01L21/321 ,  C09G1/02 ,  H01L21/768

Abstract: Methods of manufacturing a chemical-mechanical polishing (CMP) slurry and methods of performing CMP process on a substrate comprising metal features are described herein. The CMP slurry may be manufactured using a balanced concentration ratio of chelator additives to inhibitor additives, the ratio being determined based on an electro potential (Ev) value of a metal material of the substrate. The CMP process may be performed on the substrate based on the balanced concentration ratio of chelator additives to inhibitor additives of the CMP slurry.