公开(公告)号：US20150092314A1

公开(公告)日：2015-04-02

申请号：US14039192

申请日：2013-09-27

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Young Kyu Song ,  Mario Francisco Velez ,  Jonghae Kim ,  Changhan Hobie Yun ,  Chengjie Zuo ,  Xiaonan Zhang ,  Ryan David Lane ,  Matthew Michael Nowak

IPC: H01F27/29 ,  H01F41/04 ,  H01F27/40

CPC classification number: H01F27/29 ,  H01F17/0006 ,  H01F27/40 ,  H01F2017/002 ,  H01F2017/0073 ,  Y10T29/4902

Abstract: A system includes a first connector coupled to a first surface of a substrate. The first connector enables the system to be electrically coupled to a first device external to the substrate. The system includes a second connector coupled to a second surface of the substrate. The system also includes a plurality of conductive vias extending through the substrate from the first surface to the second surface. The plurality of conductive vias surrounds the first connector and the second connector. The plurality of conductive vias is electrically coupled together to form a toroidal inductor. A first lead of the toroidal inductor is electrically coupled to the first connector. A second lead of the toroidal inductor is electrically coupled to the second connector.

Abstract translation: 系统包括耦合到衬底的第一表面的第一连接器。 第一连接器使得系统能够电耦合到衬底外部的第一器件。 该系统包括耦合到基板的第二表面的第二连接器。 该系统还包括从第一表面延伸穿过基底的多个导电通孔到第二表面。 多个导电通孔围绕第一连接器和第二连接器。 多个导电通孔电耦合在一起以形成环形电感器。 环形电感器的第一引线电耦合到第一连接器。 环形电感器的第二引线电耦合到第二连接器。

公开(公告)号：US11024454B2

公开(公告)日：2021-06-01

申请号：US15191203

申请日：2016-06-23

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Mario Francisco Velez ,  Changhan Hobie Yun ,  Niranjan Sunil Mudakatte ,  Jonghae Kim ,  Chengjie Zuo ,  David Francis Berdy

IPC: H01F5/00 ,  H01F27/28 ,  H01F41/04 ,  H03H7/01 ,  H03F15/00 ,  H01F17/00 ,  H01F27/24

Abstract: Disclosed is an inductor device including a first curved metal plate, a second curved metal plate below and substantially vertically aligned with the first curved metal plate, and a first elongated via vertically aligned between the first curved metal plate and the second curved metal plate, the first elongated via configured to conductively couple the first curved metal plate to the second curved metal plate and having an aspect ratio of a width to a height of the first elongated via of at least approximately 2 to 1.

公开(公告)号：US10325855B2

公开(公告)日：2019-06-18

申请号：US15074750

申请日：2016-03-18

Applicant: QUALCOMM Incorporated

Inventor： Daeik Kim ,  Jie Fu ,  Changhan Yun ,  Chin-Kwan Kim ,  Manuel Aldrete ,  Chengjie Zuo ,  Mario Velez ,  Jonghae Kim

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00

Abstract: A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.

公开(公告)号：US10049815B2

公开(公告)日：2018-08-14

申请号：US15167782

申请日：2016-05-27

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Jonghae Kim ,  Chengjie Zuo ,  Mario Francisco Velez ,  Changhan Hobie Yun

IPC: H01F41/04 ,  H01F27/28 ,  H01F41/00 ,  H01F17/00

Abstract: A 3D nested transformer includes a substrate having a set of through substrate vias daisy chained together with a set of traces. At least some of the through substrate vias have first and second conductive regions. The set of traces also includes a first set of traces coupling together at least some of the first conductive regions of the through substrate vias, and a second set of traces coupling together at least some of the second conductive regions of the through substrate vias.

公开(公告)号：US10039188B2

公开(公告)日：2018-07-31

申请号：US14811813

申请日：2015-07-28

Applicant: QUALCOMM Incorporated

Inventor： Changhan Yun ,  Francesco Carobolante ,  Chengjie Zuo ,  Jonghae Kim ,  Mario Francisco Velez ,  Lawrence D. Smith ,  Matthew M. Nowak

IPC: H05K1/16 ,  H05K1/02 ,  H01L23/498 ,  H05K7/10 ,  H05K3/10 ,  H05K3/30 ,  H05K3/00

CPC classification number: H05K1/165 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/0243 ,  H05K1/0262 ,  H05K3/0091 ,  H05K3/10 ,  H05K3/30 ,  H05K7/1092 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49147 ,  Y10T29/49156

Abstract: A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator.

公开(公告)号：US10038422B2

公开(公告)日：2018-07-31

申请号：US15247803

申请日：2016-08-25

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  Je-Hsiung Lan ,  Chengjie Zuo ,  David Berdy ,  Jonghae Kim ,  Mario Velez ,  Niranjan Sunil Mudakatte ,  Shiqun Gu

IPC: H03H9/205 ,  H03H3/04 ,  H01L41/332 ,  H03H9/54 ,  H03H3/02

CPC classification number: H03H9/205 ,  H01L41/332 ,  H03H3/04 ,  H03H9/173 ,  H03H9/54 ,  H03H2003/021 ,  H03H2003/0435 ,  H03H2003/0442 ,  H03H2003/0471

Abstract: A single-die multi-FBAR (film bulk acoustic resonator) device includes multiple FBARs having different resonant frequencies formed over a single substrate. The FBARs include piezoelectric layers having different thicknesses but with upper electrodes formed at a same height over the substrate, lower electrodes at different heights over the substrate, and different sized air gaps separating the lower electrodes from the substrate.

公开(公告)号：US20180047673A1

公开(公告)日：2018-02-15

申请号：US15235790

申请日：2016-08-12

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Chengjie Zuo ,  Steve Fanelli ,  Husnu Ahmet Masaracioglu

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/07 ,  H01L25/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/56 ,  H03H1/00 ,  H01L23/66

CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/19 ,  H01L24/24 ,  H01L24/97 ,  H01L25/072 ,  H01L25/50 ,  H01L2223/6661 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/19101 ,  H01L2924/30111 ,  H03H1/0007 ,  H03H2001/0021 ,  H01L2224/83005

Abstract: A package includes a redistribution portion, a first portion, and a second portion. The first portion is coupled to the redistribution portion. The first portion includes a first switch comprising a plurality of switch interconnects, and a first encapsulation layer that at least partially encapsulates the first switch. The second portion is coupled to the first portion. The second portion includes a first plurality of filters. Each filter includes a plurality of filter interconnects. The second portion also includes a second encapsulation layer that at least partially encapsulates the first plurality of filters. The first portion includes a second switch positioned next to the first switch, where the first encapsulation layer at least partially encapsulates the second switch. The second portion includes a second plurality of filters positioned next to the first plurality of filters, where the second encapsulation layer at least partially encapsulates the second plurality of filters.

公开(公告)号：US09875848B2

公开(公告)日：2018-01-23

申请号：US14976973

申请日：2015-12-21

Applicant: QUALCOMM Incorporated

Inventor： David Francis Berdy ,  Daeik Daniel Kim ,  Niranjan Sunil Mudakatte ,  Je-Hsiung Jeffrey Lan ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H01G4/30 ,  H01L23/52 ,  H01G4/01 ,  H01G4/33 ,  H01L23/522 ,  H01L27/08 ,  H01L29/94 ,  H01L49/02

CPC classification number: H01G4/30 ,  H01G4/01 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/86 ,  H01L28/87 ,  H01L29/94

Abstract: An exemplary MIM capacitor may include a first metal plate, a dielectric layer on the first metal plate, a second metal plate on the dielectric layer, a via layer on the second metal plate, and a third metal plate on the via layer where the second metal plate has a tapered outline with a first side and a second side longer than the first side such that the second side provides a lower resistance path for a current flow.

公开(公告)号：US09780048B1

公开(公告)日：2017-10-03

申请号：US15227919

申请日：2016-08-03

Applicant: QUALCOMM Incorporated

Inventor： David Francis Berdy ,  Changhan Hobie Yun ,  Chengjie Zuo ,  Niranjan Sunil Mudakatte ,  Mario Francisco Velez ,  Shiqun Gu ,  Jonghae Kim

IPC: H01L21/60 ,  H01L23/66 ,  H01L23/64 ,  H01L23/00 ,  H01L25/18 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L23/66 ,  H01L23/5384 ,  H01L23/642 ,  H01L23/645 ,  H01L24/13 ,  H01L24/45 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/48195 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/19105 ,  H05K1/0243 ,  H05K1/025 ,  H05K1/141

Abstract: An integrated circuit device includes a first substrate having a ground plane. The integrated circuit device also includes a second substrate. The second substrate has a first layer of passive devices. The passive devices include at least one inductor on a first side of the second substrate. The first layer of passive devices is substantially orthogonal to the ground plane and the second substrate supported by the first substrate. An inductor magnetic field is substantially parallel to the ground plane.

公开(公告)号：US09773862B2

公开(公告)日：2017-09-26

申请号：US15375137

申请日：2016-12-11

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  Daeik Daniel Kim ,  Chengjie Zuo ,  Jonghae Kim ,  Mario Francisco Velez ,  Donald William Kidwell, Jr. ,  Jon Bradley Lasiter ,  Kwan-Yu Lai ,  Jitae Kim ,  Ravindra Vaman Shenoy

IPC: H01L21/4763 ,  H01L49/02 ,  H01L27/08 ,  H01L23/48 ,  H01L21/28 ,  H01L21/768

CPC classification number: H01L28/90 ,  H01G4/012 ,  H01G4/33 ,  H01L21/28282 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/12 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are space-efficient capacitors that have a higher quality factor than conventional designs and improve coupling of electrical energy from a through-glass via (TGV) to a dielectric. For example, provided is a TGV having a non-rectangular cross-section, where one end of the TGV is coupled to a first metal plate. A dielectric material is formed on the first metal plate. A second metal plate is formed on the dielectric material in a manner that overlaps at least a portion of the first metal plate to form at least one overlapped region of the dielectric material. At least a part of the perimeter of the overlapped region is non-planar. The overlapped region can be formed in a shape of a closed ring, in a plurality of portions of a ring shape, in substantially a quarter of a ring shape, and/or in substantially a half of a ring shape.