公开(公告)号：US11841757B1

公开(公告)日：2023-12-12

申请号：US17499241

申请日：2021-10-12

Applicant: Kepler Computing Inc.

Inventor： Amrita Mathuriya ,  Christopher B. Wilkerson ,  Rajeev Kumar Dokania ,  Debo Olaosebikan ,  Sasikanth Manipatruni

IPC: G06F1/32 ,  G06F1/329 ,  G06F1/3287

CPC classification number: G06F1/329 ,  G06F1/3287

Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

公开(公告)号：US11823725B1

公开(公告)日：2023-11-21

申请号：US17359295

申请日：2021-06-25

Applicant: Kepler Computing Inc.

Inventor： Christopher B. Wilkerson ,  Sasikanth Manipatruni ,  Rajeev Kumar Dokania ,  Amrita Mathuriya

IPC: G11C11/00 ,  G11C11/22 ,  G06F12/02 ,  G11C13/00 ,  G11C11/02

CPC classification number: G11C11/221 ,  G06F12/0246 ,  G11C11/02 ,  G11C11/225 ,  G11C13/0035 ,  G06F2212/7202 ,  G06F2212/7211

Abstract: Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.

公开(公告)号：US11818897B1

公开(公告)日：2023-11-14

申请号：US17517298

申请日：2021-11-02

Applicant: Kepler Computing Inc.

Inventor： Rajeev Kumar Dokania ,  Noriyuki Sato ,  Tanay Gosavi ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC: G11C11/00 ,  H10B53/30

CPC classification number: H10B53/30

Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.

公开(公告)号：US11817859B1

公开(公告)日：2023-11-14

申请号：US17645913

申请日：2021-12-23

Applicant: Kepler Computing Inc.

Inventor： Sasikanth Manipatruni ,  Nabil Imam ,  Ikenna Odinaka ,  Rafael Rios ,  Rajeev Kumar Dokania ,  Amrita Mathuriya

IPC: H03K19/23 ,  H03K19/0948 ,  H03K19/08

CPC classification number: H03K19/23 ,  H03K19/0813 ,  H03K19/0948

Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1 V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.

公开(公告)号：US11785782B1

公开(公告)日：2023-10-10

申请号：US17346094

申请日：2021-06-11

Applicant: Kepler Computing Inc.

Inventor： Noriyuki Sato ,  Tanay Gosavi ,  Niloy Mukherjee ,  Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC: H10B53/40

CPC classification number: H10B53/40

Abstract: A process integration and patterning flow used to pattern a memory array area for an embedded memory without perturbing a fabricating process for logic circuitries. The fabrication process uses a pocket mask (e.g., a hard mask) to decouple the etching process of a memory array area and non-memory area. Such decoupling allows for a simpler fabrication process with little to no impact on the current fabrication process. The fabrication process may use multiple pocket masks to decouple the etching process of the memory array area and the non-memory area. This fabrication process (using multiple pocket masks) allows to avoid exposure of memory material into a second pocket etch chamber. The process of etching memory material is decoupled from the process of etching an encapsulation material. Examples of embedded memory include dynamic random-access memory and ferroelectric random-access memory.

公开(公告)号：US11769790B2

公开(公告)日：2023-09-26

申请号：US17649665

申请日：2022-02-01

Applicant: Kepler Computing Inc.

Inventor： Niloy Mukherjee ,  Somilkumar J. Rathi ,  Jason Y. Wu ,  Pratyush Pandey ,  Zeying Ren ,  Fnu Atiquzzaman ,  Gabriel Antonio Paulius Velarde ,  Noriyuki Sato ,  Mauricio Manfrini ,  Tanay Gosavi ,  Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Ramamoorthy Ramesh ,  Sasikanth Manipatruni

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/535 ,  H01L23/538 ,  H01L49/02 ,  H01L21/324 ,  H01L21/768 ,  H10B53/30 ,  H10N70/00

CPC classification number: H01L28/57 ,  H01L21/324 ,  H01L21/76832 ,  H01L28/65 ,  H01L28/75 ,  H10B53/30 ,  H10N70/8836

Abstract: A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.

公开(公告)号：US11758738B2

公开(公告)日：2023-09-12

申请号：US17663187

申请日：2022-05-12

Applicant: Kepler Computing Inc.

Inventor： Sasikanth Manipatruni ,  Rajeev Kumar Dokania ,  Ramamoorthy Ramesh ,  Gaurav Thareja ,  Amrita Mathuriya

IPC: H10B53/30 ,  G11C11/22 ,  H01L49/02

CPC classification number: H10B53/30 ,  G11C11/221 ,  H01L28/56

Abstract: Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.

公开(公告)号：US11757452B1

公开(公告)日：2023-09-12

申请号：US17659992

申请日：2022-04-20

Applicant: Kepler Computing Inc.

Inventor： Amrita Mathuriya ,  Rafael Rios ,  Ikenna Odinaka ,  Darshak Doshi ,  Rajeev Kumar Dokania ,  Sasikanth Manipatruni

IPC: H03K19/23 ,  H03K19/20 ,  H01L49/02

CPC classification number: H03K19/23 ,  H01L28/55 ,  H03K19/20

Abstract: A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.

公开(公告)号：US20230246064A1

公开(公告)日：2023-08-03

申请号：US17649899

申请日：2022-02-03

Applicant: Kepler Computing Inc.

Inventor： Niloy Mukherjee ,  Somilkumar J. Rathi ,  Jason Y. Wu ,  Pratyush Pandey ,  Zeying Ren ,  FNU Atiquzzaman ,  Gabriel Antonio Paulius Velarde ,  Noriyuki Sato ,  Mauricio Manfrini ,  Tanay Gosavi ,  Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Ramamoorthy Ramesh ,  Sasikanth Manipatruni

IPC: H01L49/02 ,  H01L21/324 ,  H01L21/768 ,  H01L27/11507 ,  H01L45/00

CPC classification number: H01L28/75 ,  H01L21/324 ,  H01L21/76832 ,  H01L27/11507 ,  H01L28/57 ,  H01L28/65 ,  H01L45/147

Abstract: A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.

公开(公告)号：US11694940B1

公开(公告)日：2023-07-04

申请号：US17478841

申请日：2021-09-17

Applicant: Kepler Computing Inc.

Inventor： Amrita Mathuriya ,  Christopher B. Wilkerson ,  Rajeev Kumar Dokania ,  Debo Olaosebikan ,  Sasikanth Manipatruni

IPC: H10B53/20 ,  H01L23/367 ,  H01L23/538 ,  H01L23/48 ,  H01L23/498 ,  H01L25/16 ,  G11C5/04 ,  H01L23/00 ,  H10B51/20 ,  H10B51/40 ,  H10B53/40 ,  G06N20/00

CPC classification number: H01L23/3675 ,  G11C5/04 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/162 ,  H10B51/20 ,  H10B51/40 ,  H10B53/20 ,  H10B53/40 ,  G06N20/00 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/14335

Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.