公开(公告)号：US20050156218A1

公开(公告)日：2005-07-21

申请号：US11039745

申请日：2005-01-18

申请人： Thomas Nirschl ,  Alexander Olbrich ,  Martin Ostermayr

发明人： Thomas Nirschl ,  Alexander Olbrich ,  Martin Ostermayr

IPC分类号： H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L27/1087 ,  H01L27/10835 ,  H01L29/66181 ,  H01L29/945

摘要： A semiconductor memory cell and an associated fabrication method are provided in which a storage capacitor is connected to a selection transistor. The storage capacitor is formed in a trench of a semiconductor substrate. At the trench surface, a capacitor dielectric and an electrically conductive filling layer are formed thereon for realization of a capacitor counterelectrode. The filling layer has a projection that extends outside the trench as far as the drain region and is electrically connected thereto.

摘要翻译： 提供了一种半导体存储单元和相关的制造方法，其中存储电容器连接到选择晶体管。 存储电容器形成在半导体衬底的沟槽中。 在沟槽表面上形成电容器电介质和导电填充层，用于实现电容器对电极。 填充层具有在沟槽外延伸到漏极区域并与其电连接的突起。

公开(公告)号：US09070439B2

公开(公告)日：2015-06-30

申请号：US13426019

申请日：2012-03-21

申请人： Berndt Gammel ,  Thomas Nirschl ,  Gerd Dirscherl ,  Philip Schlazer

发明人： Berndt Gammel ,  Thomas Nirschl ,  Gerd Dirscherl ,  Philip Schlazer

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/0059 ,  G11C13/0004 ,  G11C13/0069

摘要： One or more embodiments relate to an electronic device comprising a circuitry and a programmable resistive element. The programmable resistive element comprises a first and a second state, wherein the programmable resistive element is configured to allow switching from the second state into the first state in response to a signal comprising at least a predefined level. The circuitry is configured to provide signals up the predefined level, wherein the circuitry is configured to provide a switch signal to the programmable resistive element, wherein the switch signal causes switching from the first into the second state.

摘要翻译： 一个或多个实施例涉及包括电路和可编程电阻元件的电子设备。 可编程电阻元件包括第一和第二状态，其中可编程电阻元件被配置为允许响应于包括至少预定义电平的信号从第二状态切换到第一状态。 该电路被配置为提供上述预定义电平的信号，其中电路被配置为向可编程电阻元件提供开关信号，其中开关信号引起从第一状态切换到第二状态。

公开(公告)号：US08629500B2

公开(公告)日：2014-01-14

申请号：US11816822

申请日：2005-12-09

申请人： Juergen Holz ,  Ronald Kakoschke ,  Thomas Nirschl ,  Christian Pacha ,  Klaus Schruefer ,  Thomas Schulz ,  Doris Schmitt-Landsiedel

发明人： Juergen Holz ,  Ronald Kakoschke ,  Thomas Nirschl ,  Christian Pacha ,  Klaus Schruefer ,  Thomas Schulz ,  Doris Schmitt-Landsiedel

IPC分类号： H01L29/06

CPC分类号： H01L27/0886 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/1052 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/7392 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7854 ,  H01L29/7856

摘要： An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD1) in comparison with other transistors (T2) on the same integrated circuit arrangement (10). As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions (D1, S1) of the tunnel field effect transistor.

摘要翻译： 具体地说，具有与同一集成电路装置（10）上的其它晶体管（T2）相比具有较厚栅极电介质（GD1）的隧道场效应晶体管的解释。 作为替代或另外，所述隧道场效应晶体管具有在沟道形成区域的相对远侧的栅极区域或隧道场效应晶体管的连接区域（D1，S1）之间的界面。

公开(公告)号：US08384429B2

公开(公告)日：2013-02-26

申请号：US12761812

申请日：2010-04-16

申请人： Berndt Gammel ,  Thomas Nirschl ,  Gerd Dirscherl ,  Philip Schlazer ,  Stefan Rueping

发明人： Berndt Gammel ,  Thomas Nirschl ,  Gerd Dirscherl ,  Philip Schlazer ,  Stefan Rueping

IPC分类号： H03K19/20

CPC分类号： H03K19/20 ,  G11C13/0004 ,  H01L27/24

摘要： An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates. The one or more control elements have one or more programmable resistance elements and/or one or more threshold switching elements.

摘要翻译： 集成电路具有一个或多个逻辑门和控制电路。 控制电路具有耦合到逻辑门的一个或多个控制元件。 控制电路控制一个或多个逻辑门的状态。 一个或多个控制元件具有一个或多个可编程电阻元件和/或一个或多个阈值开关元件。

公开(公告)号：US08344429B2

公开(公告)日：2013-01-01

申请号：US12212097

申请日：2008-09-17

申请人： Jan Otterstedt ,  Thomas Nirschl ,  Michael Bollu ,  Wolf Allers

发明人： Jan Otterstedt ,  Thomas Nirschl ,  Michael Bollu ,  Wolf Allers

IPC分类号： H01L23/52

CPC分类号： H01L23/52 ,  G11C5/063 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11587 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention describe compact memory arrays. In one embodiment, the memory cell array includes first, second, and third gate lines disposed over a substrate, the second gate lines are disposed between the first and the third gate lines. The first, the second, and the third gate lines form adjacent gate lines of the memory cell array. The memory cell array further includes first metal lines disposed over the first gate lines, the first metal lines coupled to the first gate lines; second metal lines disposed over the second gate lines, the second metal lines coupled to the second gate lines; and third metal lines disposed over the third gate lines, the third metal lines coupled to the third gate lines. The first metal lines, the second metal lines and the third metal lines are disposed in different metallization levels.

公开(公告)号：US08243532B2

公开(公告)日：2012-08-14

申请号：US12702759

申请日：2010-02-09

申请人： Thomas Nirschl ,  Christoph Bukethal ,  Jan Otterstedt

发明人： Thomas Nirschl ,  Christoph Bukethal ,  Jan Otterstedt

IPC分类号： G11C7/22

CPC分类号： G11C16/10 ,  G11C8/08

摘要： A structure and method for increasing the operating speed and reducing the overall programming time of a memory array are provided herein. The method and structure reduce the maximum write current consumption, for writing a plurality of data bits to a NVM array, by writing the data bits sharing an activated word line at different times (e.g., activating bit lines associated with an activated word line at different times). The write operation of respective data bits, which individually utilize only a fraction of the overall write window of the bits, are interleaved so that the maximum write current of respective bits are offset in time from the maximum write current of another bit, allowing a larger number of data bits to be written without exceeding system specifications (e.g., maximum current) and reducing overall memory write time.

摘要翻译： 本文提供了用于增加操作速度并减少存储器阵列的整体编程时间的结构和方法。 该方法和结构通过在不同时间写入共享激活字线的数据位（例如，激活与不同的激活字线相关联的位线）来减少用于将多个数据位写入NVM阵列的最大写入电流消耗 次）。 单独利用比特的整个写入窗口的一部分的各个数据位的写入操作被交织，使得各个比特的最大写入电流在时间上偏离另一个比特的最大写入电流，允许更大的 要写入的数据位数不超过系统规格（例如最大电流），并减少总体存储器写入时间。

公开(公告)号：US20120176833A1

公开(公告)日：2012-07-12

申请号：US13426019

申请日：2012-03-21

申请人： Berndt Gammel ,  Thomas Nirschl ,  Gerd Dirscherl ,  Philip Schlazer

发明人： Berndt Gammel ,  Thomas Nirschl ,  Gerd Dirscherl ,  Philip Schlazer

IPC分类号： G11C11/00

CPC分类号： G11C13/0059 ,  G11C13/0004 ,  G11C13/0069

摘要： One or more embodiments relate to an electronic device comprising a circuitry and a programmable resistive element. The programmable resistive element comprises a first and a second state, wherein the programmable resistive element is configured to allow switching from the second state into the first state in response to a signal comprising at least a predefined level. The circuitry is configured to provide signals up the predefined level, wherein the circuitry is configured to provide a switch signal to the programmable resistive element, wherein the switch signal causes switching from the first into the second state.

摘要翻译： 一个或多个实施例涉及包括电路和可编程电阻元件的电子设备。 可编程电阻元件包括第一和第二状态，其中可编程电阻元件被配置为允许响应于包括至少预定义电平的信号从第二状态切换到第一状态。 该电路被配置为提供上述预定义电平的信号，其中电路被配置为向可编程电阻元件提供开关信号，其中开关信号引起从第一状态切换到第二状态。

公开(公告)号：US20110228611A1

公开(公告)日：2011-09-22

申请号：US13116203

申请日：2011-05-26

申请人： Thomas Nirschl

发明人： Thomas Nirschl

IPC分类号： G11C16/24 ,  H03K3/00

CPC分类号： G11C7/12 ,  G11C16/24

摘要： In one embodiment, a bit-line driver has a first driver having a source terminal coupled to a high-voltage supply bus and a drain terminal coupled to the bit-line, and a second driver having a source terminal coupled to a high-voltage return bus and a drain terminal coupled to the bit line. The bit-line driver also has a first pre-driver coupled to a gate terminal of the first driver and a second pre-driver coupled to a gate terminal of the second driver. The first and second drivers use a first type of transistor, and the first and second pre-drivers use a second type of transistor. The first type of transistor is rated at a higher voltage than the second type of transistor.

摘要翻译： 在一个实施例中，位线驱动器具有第一驱动器，其具有耦合到高压电源总线的源极端子和耦合到位线的漏极端子，以及具有耦合到高电压的源极端子的第二驱动器 返回总线和耦合到位线的漏极端子。 位线驱动器还具有耦合到第一驱动器的栅极端子的第一预驱动器和耦合到第二驱动器的栅极端子的第二预驱动器。 第一和第二驱动器使用第一类晶体管，第一和第二预驱动器使用第二类晶体管。 第一种晶体管的额定电压高于第二类晶体管。

公开(公告)号：US08009481B2

公开(公告)日：2011-08-30

申请号：US12390959

申请日：2009-02-23

申请人： Thomas Nirschl

发明人： Thomas Nirschl

IPC分类号： G11C16/04

CPC分类号： G11C7/12 ,  G11C16/24

摘要： In one embodiment, a bit-line driver has a first driver having a source terminal coupled to a high-voltage supply bus and a drain terminal coupled to the bit-line, and a second driver having a source terminal coupled to a high-voltage return bus and a drain terminal coupled to the bit line. The bit-line driver also has a first pre-driver coupled to a gate terminal of the first driver and a second pre-driver coupled to a gate terminal of the second driver. The first and second drivers use a first type of transistor, and the first and second pre-drivers use a second type of transistor. The first type of transistor is rated at a higher voltage than the second type of transistor.

摘要翻译： 在一个实施例中，位线驱动器具有第一驱动器，其具有耦合到高压电源总线的源极端子和耦合到位线的漏极端子，以及具有耦合到高电压的源极端子的第二驱动器 返回总线和耦合到位线的漏极端子。 位线驱动器还具有耦合到第一驱动器的栅极端子的第一预驱动器和耦合到第二驱动器的栅极端子的第二预驱动器。 第一和第二驱动器使用第一类晶体管，第一和第二预驱动器使用第二类晶体管。 第一种晶体管的额定电压高于第二类晶体管。

公开(公告)号：US07995381B2

公开(公告)日：2011-08-09

申请号：US12258913

申请日：2008-10-27

申请人： Thomas Nirschl ,  Jan Otterstedt

发明人： Thomas Nirschl ,  Jan Otterstedt

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0064 ,  G11C13/0069

摘要： A method of operating an integrated circuit includes determining a resistance value of at least one resistivity-changing memory cell when the memory cell is in a low-resistance state, the at least one resistivity-changing memory cell configured to be programmable to at least the low-resistance state and a high-resistance state, comparing the resistance value to a threshold value, selecting, based on the comparison, a cell reset process to be employed for programming the at least one resistivity-changing memory cell to the high-resistance state. The selecting includes selecting a predetermined reset process as the cell reset process when the resistance value is less than the threshold value, and adjusting the predetermined process and selecting the adjusted predetermined reset process as the cell reset process when the resistance value is at least equal to the threshold value.

摘要翻译： 一种操作集成电路的方法包括当存储器单元处于低电阻状态时确定至少一个电阻率变化存储单元的电阻值，该至少一个电阻率变化存储单元被配置为至少可编程 低电阻状态和高电阻状态，将电阻值与阈值进行比较，基于比较，选择要用于将至少一个电阻率变化存储单元编程为高电阻的单元复位处理 州。 选择包括当电阻值小于阈值时选择预定的复位处理作为单元重置处理，并且当电阻值至少等于该值时，调整预定处理并选择调整的预定复位处理作为单元重置处理 阈值。