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    Semiconductor memory cell and associated fabrication method
    3.
    发明授权
    Semiconductor memory cell and associated fabrication method 有权
    半导体存储单元及相关制造方法

    公开(公告)号：US07304342B2

    公开(公告)日：2007-12-04

    申请号：US11039745

    申请日：2005-01-18

    申请人： Thomas Nirschl ,  Alexander Olbrich ,  Martin Ostermayr

    发明人： Thomas Nirschl ,  Alexander Olbrich ,  Martin Ostermayr

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/1087 ,  H01L27/10835 ,  H01L29/66181 ,  H01L29/945

    摘要： A semiconductor memory cell and an associated fabrication method are provided in which a storage capacitor is connected to a selection transistor. The storage capacitor is formed in a trench of a semiconductor substrate. At the trench surface, a capacitor dielectric and an electrically conductive filling layer are formed thereon for realization of a capacitor counterelectrode. The filling layer has a projection that extends outside the trench as far as the drain region and is electrically connected thereto.

    摘要翻译： 提供了一种半导体存储单元和相关的制造方法，其中存储电容器连接到选择晶体管。 存储电容器形成在半导体衬底的沟槽中。 在沟槽表面上形成电容器电介质和导电填充层，用于实现电容器对电极。 填充层具有在沟槽外延伸到漏极区域并与其电连接的突起。

    Semiconductor memory cell and associated fabrication method
    4.
    发明申请
    Semiconductor memory cell and associated fabrication method 有权
    半导体存储单元及相关制造方法

    公开(公告)号：US20050156218A1

    公开(公告)日：2005-07-21

    申请号：US11039745

    申请日：2005-01-18

    申请人： Thomas Nirschl ,  Alexander Olbrich ,  Martin Ostermayr

    发明人： Thomas Nirschl ,  Alexander Olbrich ,  Martin Ostermayr

    IPC分类号： H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/1087 ,  H01L27/10835 ,  H01L29/66181 ,  H01L29/945

    摘要： A semiconductor memory cell and an associated fabrication method are provided in which a storage capacitor is connected to a selection transistor. The storage capacitor is formed in a trench of a semiconductor substrate. At the trench surface, a capacitor dielectric and an electrically conductive filling layer are formed thereon for realization of a capacitor counterelectrode. The filling layer has a projection that extends outside the trench as far as the drain region and is electrically connected thereto.

    摘要翻译： 提供了一种半导体存储单元和相关的制造方法，其中存储电容器连接到选择晶体管。 存储电容器形成在半导体衬底的沟槽中。 在沟槽表面上形成电容器电介质和导电填充层，用于实现电容器对电极。 填充层具有在沟槽外延伸到漏极区域并与其电连接的突起。

    Bit line dummy core-cell and method for producing a bit line dummy core-cell
    7.
    发明授权
    Bit line dummy core-cell and method for producing a bit line dummy core-cell 有权

    公开(公告)号：US07394682B2

    公开(公告)日：2008-07-01

    申请号：US11586176

    申请日：2006-10-25

    申请人： Martin Ostermayr ,  Christophe Chanussot ,  Vincent Gouin ,  Alexander Olbrich

    发明人： Martin Ostermayr ,  Christophe Chanussot ,  Vincent Gouin ,  Alexander Olbrich

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412 ,  G11C11/413

    摘要： A bit line dummy core-cell comprises at least a first inverter and at least a second inverter which are cross coupled to form a bistable flip-flop. The first inverter comprises a first PMOS transistor and a first NMOS transistor connected in series by means of a first internal storage node between a high reference potential and a low reference potential. The second inverter comprises a second PMOS transistor and a second NMOS transistor connected in series by means of a second internal storage node. The source of the second PMOS transistor and the second internal storage node are connected to the low reference potential so that the first internal storage node always stores a logic high level. A first access transistor is coupled between a dummy bit line providing a self-timing signal and the first internal node storing the logical high level.

    Bit line dummy core-cell and method for producing a bit line dummy core-cell
    8.
    发明申请
    Bit line dummy core-cell and method for producing a bit line dummy core-cell 有权
    位线虚拟核心单元和产生位线虚拟核心单元的方法

    公开(公告)号：US20080112245A1

    公开(公告)日：2008-05-15

    申请号：US11586176

    申请日：2006-10-25

    申请人： Martin Ostermayr ,  Christophe Chanussot ,  Vincent Gouin ,  Alexander Olbrich

    发明人： Martin Ostermayr ,  Christophe Chanussot ,  Vincent Gouin ,  Alexander Olbrich

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412 ,  G11C11/413

    摘要： A bit line dummy core-cell comprises at least a first inverter and at least a second inverter which are cross coupled to form a bistable flip-flop. The first inverter comprises a first PMOS transistor and a first NMOS transistor connected in series by means of a first internal storage node between a high reference potential and a low reference potential. The second inverter comprises a second PMOS transistor and a second NMOS transistor connected in series by means of a second internal storage node. The source of the second PMOS transistor and the second internal storage node are connected to the low reference potential so that the first internal storage node always stores a logic high level. A first access transistor is coupled between a dummy bit line providing a self-timing signal and the first internal node storing the logical high level.

    摘要翻译： 位线虚拟核心单元包括交叉耦合以形成双稳态触发器的至少第一反相器和至少第二反相器。 第一反相器包括通过第一内部存储节点在高参考电位和低参考电位之间串联连接的第一PMOS晶体管和第一NMOS晶体管。 第二反相器包括通过第二内部存储节点串联连接的第二PMOS晶体管和第二NMOS晶体管。 第二PMOS晶体管和第二内部存储节点的源极连接到低参考电位，使得第一内部存储节点总是存储逻辑高电平。 第一存取晶体管耦合在提供自定时信号的伪位线和存储逻辑高电平的第一内部节点之间。

    Method and device for correcting errors in a digital memory
    9.
    发明申请
    Method and device for correcting errors in a digital memory 审中-公开
    用于校正数字存储器中的错误的方法和装置

    公开(公告)号：US20050066224A1

    公开(公告)日：2005-03-24

    申请号：US10901927

    申请日：2004-07-29

    申请人： Mario Di Ronza ,  Alexander Olbrich

    发明人： Mario Di Ronza ,  Alexander Olbrich

    IPC分类号： G06F11/00 ,  G11C29/00

    CPC分类号： G11C29/76 ,  G11C29/846

    摘要： A correcting device (6) with substitute memory words (8) which take on the function of memory words identified as defective in the memory (1) is assigned for correcting the errors of a digital memory (1). Memory access to memory words of the memory (1) identified as defective is for this purpose diverted to corresponding substitute memory words (8). According to the invention the memory (1) has different lines (2, 3) for reading and for writing, wherein when there is write access a value written into a memory word via an input line (2) is read out again and appears on the output line (3) (write-through memory). Each time there is write access to a memory word of the memory (1) the written value is compared with the value output via the output line (3) and if there is incorrect agreement the corresponding memory word is identified as defective. In this way error correction can take place during normal operation of the memory (1) (at-speed correction), no checking of the memory word being necessary at the start. Each memory word of the memory (1) is checked each time there is write access and, if applicable, identified as defective, whereupon the error can be corrected with the aid of a substitute memory word (8).

    摘要翻译： 分配具有替代存储字（8）的校正装置（6），其具有在存储器（1）中识别为缺陷的存储器字的功能，用于校正数字存储器（1）的错误。 识别为有缺陷的存储器（1）的存储器字的存储器访问为此被转移到相应的替代存储字（8）。 根据本发明，存储器（1）具有用于读取和写入的不同的线（2,3），其中当存在写入时，经由输入线（2）写入存储器字的值被再次读出并出现在 输出线（3）（直写存储器）。 每次对存储器（1）的存储器字进行写入访问时，将写入值与经由输出线（3）输出的值进行比较，并且如果存在不正确的一致性，则将相应的存储器字识别为有缺陷。 以这种方式，可以在存储器（1）的正常操作期间进行错误校正（速度校正），在开始时不需要检查存储器字。 存储器（1）的每个存储器字在每次存取写访问时被检查，并且如果适用，则被识别为有缺陷的，因此可以借助替代存储字（8）校正错误。