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公开(公告)号：US08243532B2
公开(公告)日：2012-08-14
申请号：US12702759
申请日：2010-02-09
IPC分类号： G11C7/22
摘要： A structure and method for increasing the operating speed and reducing the overall programming time of a memory array are provided herein. The method and structure reduce the maximum write current consumption, for writing a plurality of data bits to a NVM array, by writing the data bits sharing an activated word line at different times (e.g., activating bit lines associated with an activated word line at different times). The write operation of respective data bits, which individually utilize only a fraction of the overall write window of the bits, are interleaved so that the maximum write current of respective bits are offset in time from the maximum write current of another bit, allowing a larger number of data bits to be written without exceeding system specifications (e.g., maximum current) and reducing overall memory write time.
摘要翻译： 本文提供了用于增加操作速度并减少存储器阵列的整体编程时间的结构和方法。 该方法和结构通过在不同时间写入共享激活字线的数据位（例如，激活与不同的激活字线相关联的位线）来减少用于将多个数据位写入NVM阵列的最大写入电流消耗 次）。 单独利用比特的整个写入窗口的一部分的各个数据位的写入操作被交织，使得各个比特的最大写入电流在时间上偏离另一个比特的最大写入电流，允许更大的 要写入的数据位数不超过系统规格（例如最大电流），并减少总体存储器写入时间。
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公开(公告)号：US20110194364A1
公开(公告)日：2011-08-11
申请号：US12702759
申请日：2010-02-09
摘要： The disclosed invention provides a structure and method for increasing the operating speed and reduce the overall programming time of a memory array. In one embodiment, the method and structure provided herein reduce the maximum write current consumption, for writing a plurality of data bits to a NVM array, by writing the data bits sharing an activated word line at different times (e.g., activating bit lines associated with an activated word line at different times). Specifically, the write operation of respective data bits, which individually utilize only a fraction of the overall write window of the bits, are interleaved so that the maximum write current of respective bits are offset in time from the maximum write current of another bit. This interleaving of data bit write windows allows a larger number of data bits to be written without exceeding system specifications (e.g., maximum current) reducing overall memory write time.
摘要翻译： 所公开的发明提供了一种用于增加操作速度并减少存储器阵列的整体编程时间的结构和方法。 在一个实施例中，本文提供的方法和结构通过在不同时间写入共享激活字线的数据位（例如，激活与...相关联的位线）来减少用于将多个数据位写入NVM阵列的最大写入电流消耗 在不同时间激活字线）。 具体地说，分别仅使用比特的整个写入窗口的一部分的各个数据比特的写入操作被交织，使得各个比特的最大写入电流在时间上偏离另一个比特的最大写入电流。 数据位写入窗口的这种交错允许在不超出系统规格（例如，最大电流））的情况下写入更大数量的数据位，从而减少总体存储器写入时间。
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