公开(公告)号：US20240334714A1

公开(公告)日：2024-10-03

申请号：US18459191

申请日：2023-08-31

Applicant: SK hynix Inc.

Inventor： Sang Gu YEO ,  Yong Jin JEONG

IPC: H10B63/00 ,  H01L21/762

CPC classification number: H10B63/845 ,  H01L21/76224

Abstract: A manufacturing method may include forming an opening within a stack, forming a variable resistance layer within the opening and on the stack, forming a conductive layer on the variable resistance layer, forming a conductive pattern including a first part within the opening and a second part on the stack, by etching the conductive layer, forming a variable resistance pattern including a first part within the opening and a second part on the stack, by etching the variable resistance layer, and planarizing the conductive pattern and the variable resistance pattern until the stack is exposed.

公开(公告)号：US20240324477A1

公开(公告)日：2024-09-26

申请号：US18593589

申请日：2024-03-01

Applicant: Kioxia Corporation

Inventor： Soichiro ONO ,  Hiroyuki KANAYA

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/841 ,  H10B63/84 ,  H10N70/011 ,  H10N70/8828

Abstract: A storage device includes a memory cell that includes a variable resistance storage element and a switching element connected in series thereto and stacked therewith in a first direction, the switching element including a first electrode, a second electrode that includes a first part formed of a first material to which a first element is added, and a switching material layer that is between the first electrode and the first part of the second electrode and formed of a first insulating material to which the first element is added. The storage device further includes a first insulating layer that surrounds the switching material layer and formed of the first insulating material to which the first element is not added. An outer periphery of the first part of the second electrode and an outer periphery of the switching material layer are aligned in the first direction.

公开(公告)号：US20240324474A1

公开(公告)日：2024-09-26

申请号：US18735715

申请日：2024-06-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Der CHIH ,  Wen-Zhang LIN ,  Yun-Sheng CHEN ,  Jonathan Tsung-Yung CHANG ,  Chrong-Jung LIN ,  Ya-Chin KING ,  Cheng-Jun LIN ,  Wang-Yi LEE

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/021 ,  H10B63/80 ,  H10N70/063 ,  H10N70/066 ,  H10N70/068 ,  H10N70/841

Abstract: A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.

公开(公告)号：US12101935B2

公开(公告)日：2024-09-24

申请号：US17408149

申请日：2021-08-20

Applicant: SK hynix Inc.

Inventor： Seo Hyun Kim ,  In Ku Kang

IPC: H10B43/27 ,  H10B41/27 ,  H10B63/00

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B63/34

Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure with first material layers and second material layers that are alternately stacked with each other, forming a first opening that passes through the stacked structure, forming second openings between the first material layers, forming first sacrificial layers in the second openings, forming first isolation layers that protrude into the first opening by oxidizing the first sacrificial layers, forming mold patterns on the first material layers between the protruding portions of the first isolation layers, forming third openings by etching portions of the first isolation layers that are exposed between the mold patterns, forming second sacrificial layers in the third openings, and forming second isolation layers that protrude farther toward the center of the first opening than the mold patterns by oxidizing the second sacrificial layers.

公开(公告)号：US12075713B2

公开(公告)日：2024-08-27

申请号：US18321843

申请日：2023-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jau-Yi Wu

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/826 ,  H10B63/30 ,  H10N70/021 ,  H10N70/231 ,  H10N70/841

Abstract: A device and a method of forming the same are provided. The device includes a substrate, a first dielectric layer over the substrate, a bottom electrode extending through the first dielectric layer, a first buffer layer over the bottom electrode, a phase-change layer over the first buffer layer, a top electrode over the phase-change layer, and a second dielectric layer over the first dielectric layer. The second dielectric layer surrounds the phase-change layer and the top electrode. A width of the top electrode is greater than a width of the bottom electrode.

公开(公告)号：US12069872B2

公开(公告)日：2024-08-20

申请号：US18231304

申请日：2023-08-08

Applicant: Kioxia Corporation

Inventor： Takahiko Iizuka ,  Daisaburo Takashima ,  Ryu Ogiwara ,  Rieko Funatsuki ,  Yoshiki Kamata ,  Misako Morota ,  Yoshiaki Asao ,  Yukihiro Nomura

IPC: G11C11/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/845 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  H10B63/34 ,  H10N70/066 ,  H10N70/231 ,  H10N70/8828 ,  G11C2213/75

Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.

公开(公告)号：US20240276894A1

公开(公告)日：2024-08-15

申请号：US18646334

申请日：2024-04-25

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe BOIVIN ,  Roberto SIMOLA ,  Yohann MOUSTAPHA-RABAULT

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/231 ,  H10B63/80 ,  H10N70/021 ,  H10N70/063 ,  H10N70/066 ,  H10N70/068 ,  H10N70/882 ,  H10N70/883

Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.

公开(公告)号：US20240276891A1

公开(公告)日：2024-08-15

申请号：US18343443

申请日：2023-06-28

Applicant: SK hynix Inc.

Inventor： Woo Tae LEE ,  Su Jee KIM

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/066 ,  H10B63/84 ,  H10N70/063 ,  H10N70/8613 ,  H10N70/883

Abstract: A semiconductor device may include first conductive lines extending in a first direction; second conductive lines extending in a second direction that intersects the first direction; memory cells disposed between the first conductive lines and the second conductive lines in a third direction perpendicular to each of the first and the second directions, each of the memory cells comprising a variable resistance pattern; first gap-fill patterns disposed between the memory cells and having first thermal conductivity; and second gap-fill patterns disposed on the first gap-fill patterns in the third direction and having second thermal conductivity lower than the first thermal conductivity, wherein an interface between each of the second gap-fill patterns and each a corresponding one of the first gap-fill patterns is disposed between an upper surface and a lower surface of the variable resistance pattern.

公开(公告)号：US20240276724A1

公开(公告)日：2024-08-15

申请号：US18614945

申请日：2024-03-25

Applicant: SK hynix Inc.

Inventor： In Su PARK

IPC: H10B43/27 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/10 ,  H01L29/417 ,  H01L29/45 ,  H10B41/27 ,  H10B63/00

CPC classification number: H10B43/27 ,  H01L29/1037 ,  H01L29/41741 ,  H01L29/456 ,  H10B41/27 ,  H10B63/845 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31144 ,  H01L21/32139 ,  H01L29/40114 ,  H01L29/40117

Abstract: A semiconductor device includes a stack structure, a channel layer passing through the stack structure, a memory layer enclosing the channel layer and including first and second openings which expose the channel layer, a well plate coupled to the channel layer through the first opening, and a source plate coupled to the channel layer through the second opening.

公开(公告)号：US12063795B2

公开(公告)日：2024-08-13

申请号：US17542886

申请日：2021-12-06

Applicant: SK hynix Inc.

Inventor： Jae Hyun Han

IPC: H10B63/00 ,  G11C7/18 ,  G11C8/14 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/84 ,  G11C7/18 ,  G11C8/14 ,  H10N70/25 ,  H10N70/8833

Abstract: A semiconductor device includes a substrate, a first bit line disposed on the substrate, a first tunnel insulation layer disposed on the first bit line, a variable resistance structure disposed on the first tunnel insulation layer and having a pillar structure, a second tunnel insulation layer disposed on an upper surface of the variable resistance structure, a second bit line disposed on the second tunnel insulation layer, a barrier insulation layer disposed on a sidewall surface of the variable resistance structure, and a word line disposed on the barrier insulation layer. A dielectric constant of the barrier insulation layer is greater than a dielectric constant of each of the first and second tunnel insulation layers.