公开(公告)号：US20240339135A1

公开(公告)日：2024-10-10

申请号：US18365726

申请日：2023-08-04

申请人： SK hynix Inc.

发明人： Yong Jin JEONG ,  Sang Gu YEO

IPC分类号： G11C5/06 ,  H10B63/00 ,  H10N70/00

CPC分类号： G11C5/063 ,  H10B63/84 ,  H10N70/021 ,  H10N70/841

摘要： A semiconductor device may include a first contact plug, a word line electrically connected to the first contact plug and extending in a first direction, a second contact plug, a bit line extending in a second direction that intersects the first direction, and a memory cell disposed between the word line and the bit line and including a variable resistance layer. The bit line may include a first protruding part that protrudes into the memory cell, a second protruding part that is connected to the second contact plug, and a connection part that connects the first protruding part and the second protruding part and that extends in the second direction.

公开(公告)号：US20240334714A1

公开(公告)日：2024-10-03

申请号：US18459191

申请日：2023-08-31

申请人： SK hynix Inc.

发明人： Sang Gu YEO ,  Yong Jin JEONG

IPC分类号： H10B63/00 ,  H01L21/762

CPC分类号： H10B63/845 ,  H01L21/76224

摘要： A manufacturing method may include forming an opening within a stack, forming a variable resistance layer within the opening and on the stack, forming a conductive layer on the variable resistance layer, forming a conductive pattern including a first part within the opening and a second part on the stack, by etching the conductive layer, forming a variable resistance pattern including a first part within the opening and a second part on the stack, by etching the variable resistance layer, and planarizing the conductive pattern and the variable resistance pattern until the stack is exposed.