公开(公告)号：US10176890B2

公开(公告)日：2019-01-08

申请号：US15627173

申请日：2017-06-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alfredo Alba ,  Anni R. Coden ,  Clemens Drews ,  Daniel F. Gruhl ,  Neal R. Lewis ,  Pablo N. Mendes ,  Cartic Ramakrishnan ,  Joseph F. Terdiman

IPC: H03M5/00 ,  H03M7/00 ,  H03M7/30 ,  G16H10/60 ,  G06F17/24 ,  G10L15/26 ,  G06F3/038 ,  G06F17/22 ,  G06F17/27 ,  G06F17/21 ,  G06F17/28 ,  G06F17/30 ,  G06F3/0482

Abstract: A method comprising receiving a document having multiple sections of different types using a processor. The method also comprises obtaining a plurality of lexicons using the processor, each of the lexicons for interpreting fragments in one or more of the section types. The method further comprises interpreting fragments in a first section of the multiple sections using the processor and one or more lexicons. The method still further comprises determining, based upon the interpretation and using the processor, that a fragment in the first section is misplaced. The method still further comprises re-locating, using the processor, the misplaced fragment to a second section of the multiple sections in the document to generate a re-organized document. The method additionally includes storing the re-organized document in a hardware storage system using the processor.

公开(公告)号：US10110247B1

公开(公告)日：2018-10-23

申请号：US15846839

申请日：2017-12-19

Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC

Inventor： Cynthia D Baringer ,  Mohiuddin Ahmed ,  Jongchan Kang ,  James Chingwei Li ,  Emilio A Sovero ,  Timothy J Talty

IPC: H03M7/00 ,  H03M3/00 ,  H04B17/20 ,  H03M1/02 ,  H04B1/16 ,  H04B1/08

Abstract: A method and apparatus for temperature compensation for data converters in a software defined radio. Specifically, the system and method are teach monitoring the temperature of critical signal processing components such as band pass filters, ADCs and DACs and retrieving modulator coefficients in response to the temperatures and the like. The modulator coefficients are then used to compensate for temperature changes, performance changes and the like.

公开(公告)号：US10090856B2

公开(公告)日：2018-10-02

申请号：US15717427

申请日：2017-09-27

Applicant: GE Video Compression, LLC

Inventor： Detlev Marpe ,  Tung Nguyen ,  Heiko Schwarz ,  Thomas Wiegand

IPC: H03M7/00

Abstract: Decomposing a value range of the respective syntax elements into a sequence of n partitions with coding the components of z laying within the respective partitions separately with at least one by VLC coding and with at least one by PIPE or entropy coding is used to greatly increase the compression efficiency at a moderate coding overhead since the coding scheme used may be better adapted to the syntax element statistics. Accordingly, syntax elements are decomposed into a respective number n of source symbols si with i=1 . . . n, the respective number n of source symbols depending on as to which of a sequence of n partitions into which a value range of the respective syntax elements is sub-divided, a value z of the respective syntax elements falls into, so that a sum of values of the respective number of source symbols si yields z, and, if n>1, for all i=1 . . . n−1, the value of si corresponds to a range of the ith partition.

公开(公告)号：US10063255B2

公开(公告)日：2018-08-28

申请号：US15618530

申请日：2017-06-09

Applicant: Regents of the University of Minnesota

Inventor： Marcus Riedel ,  Devon Jenson

IPC: H03M7/00 ,  H03M7/26 ,  H04B1/16

CPC classification number: H03M7/26 ,  H04B1/16

Abstract: In some examples, a device includes an integrated circuit comprising a computational unit configured to process at least two input bit streams that each include a sequential set of data bits or two or more sets of data bits in parallel that is deterministically encoded to represent numerical values based on a probability that any data bit in the bit stream is high. In some examples, the computational unit includes a convolver configured to generate pair-wise bit combinations of the data bits of the input bit streams. In some examples, e computational unit further includes a stochastic computational unit configured to perform a computational operation on the pair-wise bit combinations and produce an output bit stream having a set of data bits indicating a result of the computational operation based on a probability that any data bit in the set of data bits of the output bit stream is high.

公开(公告)号：US10033406B2

公开(公告)日：2018-07-24

申请号：US13655466

申请日：2012-10-19

Applicant: MEDIATEK INC.

Inventor： Yu-Wen Huang ,  Xun Guo

IPC: H04N19/91 ,  H04N19/174 ,  H04N19/436 ,  H03M7/00 ,  H03M7/40

Abstract: A method for performing parallel coding with ordered entropy slices includes: providing a plurality of entropy slices to a plurality of processing elements, wherein each entropy slice includes a plurality of blocks; initializing CABAC states of a current entropy slice as the CABAC states of a previous entropy slice after processing DB blocks of the previous entropy slice. DB is a positive integer.

公开(公告)号：US09973209B2

公开(公告)日：2018-05-15

申请号：US15666817

申请日：2017-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tetsuo Kosuge ,  Doo Hyun Kim

IPC: H03M7/00 ,  H03M7/30 ,  H03M7/40

CPC classification number: H03M7/6011 ,  H03M7/4006 ,  H03M7/6005

Abstract: A processor includes a first encoder configured to encode a regular bin block including at least one regular bin, a second encoder configured to encode a bypass bin block including at least one bypass bin, and a parameter calculating module comprising parameter calculating circuitry configured to determine context information for encoding the regular bin block and to transmit the context information to the first encoder. The first encoder and the second encoder may process the regular bin block and the bypass bin block simultaneously and in parallel during at least part of a specific processing cycle.

公开(公告)号：US09900558B2

公开(公告)日：2018-02-20

申请号：US14921494

申请日：2015-10-23

Applicant: Aidmics Biotechnology Co., Ltd.

Inventor： Cheng-Ming Lin ,  Shu-Sheng Lin ,  Chang-Yu Chen ,  Tsun-Chao Chiang

IPC: H04N7/18 ,  H03M7/00 ,  G02B6/00 ,  G02B5/02 ,  G02B21/34 ,  F21V8/00 ,  G02B21/08 ,  G02B21/36

CPC classification number: H04N7/18 ,  G02B5/0278 ,  G02B6/0001 ,  G02B21/086 ,  G02B21/34 ,  G02B21/36

Abstract: A microscope module includes a light source assembly, a sampling assembly and a diffusing element. The light source assembly includes a light source and a light guide element. The light source is disposed close to the light incidence end of the light guide element. The sampling assembly includes a cover and a base. The cover and the base are combined to define a sample accommodating space, which is located at the light exit end of the light guide element. The diffusing element is disposed between the light source and the sample accommodating space. The light emitted from the light source passes through the diffusing element and then enters the sample accommodating space. A microscope device containing the microscope module is also disclosed.

公开(公告)号：US20180041196A1

公开(公告)日：2018-02-08

申请号：US15786500

申请日：2017-10-17

Applicant: Avnera Corporation

Inventor： Xudong Zhao

IPC: H03H17/06 ,  H03M13/27 ,  H03M13/00 ,  H03M7/00 ,  H03H17/02 ,  G10L21/0316 ,  G10L21/0356 ,  H03M13/33 ,  H03M5/00 ,  G10L19/00 ,  G10L19/24

CPC classification number: H03H17/0628 ,  G10L19/00 ,  G10L19/24 ,  G10L21/0316 ,  G10L21/0356 ,  G10L2019/001 ,  H03H17/028 ,  H03M5/00 ,  H03M7/00 ,  H03M13/00 ,  H03M13/27 ,  H03M13/33

Abstract: Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.

公开(公告)号：US09853660B1

公开(公告)日：2017-12-26

申请号：US15468061

申请日：2017-03-23

Applicant: INTEL CORPORATION

Inventor： Vinodh Gopal ,  Kirk S. Yap ,  Daniel F. Cutter ,  James D. Guilford ,  Wajdi K. Feghali

IPC: H03M7/00 ,  H03M7/34 ,  H03M7/30 ,  H03M7/40

CPC classification number: H03M7/3086 ,  H03M7/40 ,  H03M7/6023

Abstract: Techniques and apparatus for parallel data compression are described. An apparatus to provide parallel data compression may include at least one memory and logic for a compression component, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to provide at least one data input sequence to a plurality of compression components, determine compression information for the plurality of compression components, and perform a compression process on the at least one data input sequence via the plurality of compression components to generate at least one data output sequence, the plurality of compression components to perform the compression process in parallel based on the compression information.

公开(公告)号：US09843804B2

公开(公告)日：2017-12-12

申请号：US15532166

申请日：2015-12-09

Applicant: MediaTek Singapore Pte. Ltd.

Inventor： Jicheng An ,  Yi-Wen Chen ,  Kai Zhang

IPC: H03M7/00 ,  H04N19/119 ,  H04N19/176 ,  H04N19/174 ,  H04N19/96 ,  H04N13/00 ,  G06T9/00 ,  H04N13/02

CPC classification number: H04N19/119 ,  G06T9/005 ,  H04N13/189 ,  H04N19/147 ,  H04N19/174 ,  H04N19/176 ,  H04N19/96

Abstract: A method of video coding using block partitioning process including a binary tree partitioning process is disclosed. The block partitioning process is applied to a block of video data to partition the block into final sub-blocks. Coding process comprising prediction process, transform process or both for the block will be applied at the final sub-blocks level. The binary tree partitioning process can be applied to a given block recursively to generate binary tree leaf nodes until a termination condition is met. In another embodiment, the quadtree partitioning process is applied to a block first. The quadtree leaf nodes are further partitioned using the binary tree partitioning process. The quadtree partitioning process can be applied to a given block recursively to generate quadtree leaf nodes until a termination condition is met.