公开(公告)号：US12089419B2

公开(公告)日：2024-09-10

申请号：US18304335

申请日：2023-04-20

申请人： United Microelectronics Corp.

发明人： Cheng-Yi Lin ,  Tang Chun Weng ,  Chia-Chang Hsu ,  Yung Shen Chen ,  Chia-Hung Lin

IPC分类号： H10B61/00 ,  H01L23/522 ,  H01L23/528 ,  H10N50/01 ,  H10N50/80

CPC分类号： H10B61/00 ,  H01L23/5226 ,  H01L23/5283 ,  H10N50/01 ,  H10N50/80

摘要： Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.

公开(公告)号：US12089417B2

公开(公告)日：2024-09-10

申请号：US17459847

申请日：2021-08-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-En Huang ,  Meng-Han Lin

IPC分类号： H10B51/50 ,  H01L23/522 ,  H10B51/20 ,  H10B51/30

CPC分类号： H10B51/50 ,  H01L23/5226 ,  H10B51/20 ,  H10B51/30

摘要： Memory devices and a method of fabricating memory devices are disclosed. In one aspect, the method includes forming a plurality of first transistors in a first area and a plurality of second transistors in a second area and forming a stack over the second area. The method includes forming a memory array portion and an interface portion through the stack. The memory array portion includes memory strings and the interface portion includes first conductive structures extending along a lateral direction. The method further includes simultaneously forming second conductive structures in the first area and forming third conductive structures in the second area. The second conductive structures each vertically extend to electrically couple to at least one of the first transistors, and the third conductive structures each vertically extend through one of the memory strings to electrically couple to at least one of the second transistors.

公开(公告)号：US12087836B2

公开(公告)日：2024-09-10

申请号：US18382339

申请日：2023-10-20

申请人： Intel Corporation

发明人： Rami Hourani ,  Richard Vreeland ,  Giselle Elbaz ,  Manish Chandhok ,  Richard E. Schenker ,  Gurpreet Singh ,  Florian Gstrein ,  Nafees Kabir ,  Tristan A. Tronic ,  Eungnak Han

IPC分类号： H01L29/423 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/4238 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/41775 ,  H01L29/7851

摘要： Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.

公开(公告)号：US12087703B2

公开(公告)日：2024-09-10

申请号：US17293617

申请日：2019-11-27

申请人： Hitachi Astemo, Ltd.

发明人： Katsumi Ikegaya ,  Takayuki Oshima ,  Yoichiro Kobayashi ,  Masato Kita ,  Keishi Komoriyama ,  Minoru Migita ,  Yu Kawagoe ,  Kiyotaka Kanno

IPC分类号： H01L23/528 ,  B60R16/03 ,  H01L21/8234 ,  H01L23/00 ,  H01L23/522 ,  H01L27/088

CPC分类号： H01L23/562 ,  B60R16/03 ,  H01L21/823475 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L27/088

摘要： In a semiconductor device equipped with a current mirror circuit, a highly reliable semiconductor device capable of suppressing a change in a mirror ratio of the current mirror circuit over time is provided. A current mirror circuit that includes a first MOS transistor and a plurality of MOS transistors paired with the first MOS transistor, and a plurality of wiring layers formed on an upper layer of the MOS transistor are provided. The plurality of wiring layers are arranged such that wiring patterns have the same shape within a predetermined range from an end of a channel region of each of the first MOS transistor and the plurality of MOS transistors.

公开(公告)号：US12087687B2

公开(公告)日：2024-09-10

申请号：US17555520

申请日：2021-12-20

申请人： United Semiconductor (Xiamen) Co., Ltd.

发明人： Wei-Chun Chang ,  You-Di Jhang ,  Chin-Chun Huang ,  Wen Yi Tan

IPC分类号： H01L27/06 ,  H01L23/522 ,  H01L29/78 ,  H01L23/532 ,  H01L49/02

CPC分类号： H01L23/5228 ,  H01L27/0688 ,  H01L23/5226 ,  H01L23/53228 ,  H01L28/24

摘要： A semiconductor device includes a resistor disposed on a second etching stop layer in the resistor forming region. A fourth interlayer dielectric layer covers the resistor and the second etch stop layer. A first via is located in the fourth interlayer dielectric layer and is electrically connected to a terminal of the resistor. By forming the resistor in BEOL process, the problem of the contact stop depth difference that affects the process window and causes the reduced yield can be improved.

公开(公告)号：US20240298441A1

公开(公告)日：2024-09-05

申请号：US18476415

申请日：2023-09-28

申请人： Samsung Electronics Co., Ltd.

发明人： Hyo-Jung Kim ,  Donghoon Kwon

IPC分类号： H10B41/41 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC分类号： H10B41/41 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/06506

摘要： A semiconductor device may include a peripheral circuit structure, a source structure on the peripheral circuit structure, a first capacitor electrode on the peripheral circuit structure, an electrode insulating layer that at least partially surrounds the first capacitor electrode, a gate stack on the source structure, a memory channel structure that extends through the gate stack, a staircase insulating layer on the gate stack and the electrode insulating layer, a second capacitor electrode on the first capacitor electrode and that extends through the staircase insulating layer, and a penetration via that extends through the staircase insulating layer and the electrode insulating layer.

公开(公告)号：US20240297137A1

公开(公告)日：2024-09-05

申请号：US18660190

申请日：2024-05-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yen-Kun Lai ,  Chien-Hao Hsu ,  Wei-Hsiang Tu ,  Kuo-Chin Chang ,  Mirng-ji Lii

IPC分类号： H01L23/00 ,  H01L23/522

CPC分类号： H01L24/13 ,  H01L23/5226 ,  H01L24/05 ,  H01L2224/02206 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13017

摘要： A semiconductor die includes a semiconductor substrate, an interconnect structure, and a conductive bump. The interconnect structure is disposed on and electrically connected to the semiconductor substrate. The interconnect structure includes stacked interconnect layers. Each of the stacked interconnect layers includes a dielectric layer and an interconnect wiring embedded in the dielectric layer. The interconnect wiring of a first interconnect layer among the stacked interconnect layers further includes a first via and second vias. The first via electrically connected to the interconnect wiring. The second vias connected to the interconnect wiring, and the first via and the second vias are located on a same level height. The conductive bump is disposed on the interconnect structure. The conductive bump includes a base portion and a protruding portion connected to the base portion, and the base portion is between the protruding portion and the first via.

公开(公告)号：US20240297115A1

公开(公告)日：2024-09-05

申请号：US18333189

申请日：2023-06-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Chung Chen ,  Meng-Sheng Chang ,  Chung-Sheng Yuan ,  Yi-Kan Cheng

IPC分类号： H01L23/525 ,  G11C17/16 ,  H01L23/522 ,  H01L23/528 ,  H10B20/25

CPC分类号： H01L23/5256 ,  G11C17/16 ,  H01L23/5226 ,  H01L23/5283 ,  H10B20/25 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

摘要： A semiconductor structure includes a substrate having a first surface and a second surface opposite the first surface. The semiconductor structure includes a semiconductor device disposed on the first surface. The semiconductor structure includes a metallization layer disposed on the second surface. The semiconductor structure includes a first conductive via and a second conductive via coupled in parallel to the metallization layer, the first conductive via and the second conductive via extending from the second side toward the first side. The semiconductor structure further includes an electrical fuse disposed over the semiconductor device and coupled to the first and second conductive vias.

公开(公告)号：US20240296888A1

公开(公告)日：2024-09-05

申请号：US18653785

申请日：2024-05-02

申请人： Kioxia Corporation

发明人： Hiroshi MAEJIMA

IPC分类号： G11C16/04 ,  G11C5/06 ,  G11C7/06 ,  G11C16/08 ,  G11C16/26 ,  H01L23/522 ,  H01L23/528 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC分类号： G11C16/0483 ,  G11C5/063 ,  G11C7/06 ,  G11C16/08 ,  G11C16/26 ,  H01L23/5226 ,  H01L23/528 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

摘要： A semiconductor storage device includes word lines extending in first and second directions, and separated from each other in a third direction, sense amplifier circuits that partially overlap the word lines in the third direction, memory strings intersecting the word lines and extending in the third direction, memory-side bit lines extending in the first direction, separated from each other in the second direction, and including first and second adjacent memory-side bit lines, circuit-side bit lines between the word lines and the sense amplifier circuits and partially overlapping the respective memory-side bit lines in the third direction, and contact plugs extending in the third direction and respectively connecting the memory-side bit lines and the circuit-side bit lines. The contact plugs include first and second contract plugs that are electrically connected to the first and second memory-side bit lines, respectively, and are not aligned along the first or second direction.

公开(公告)号：US20240296273A1

公开(公告)日：2024-09-05

申请号：US18663652

申请日：2024-05-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jung-Chan YANG ,  Ting-Wei CHIANG ,  Jerry Chang-Jui KAO ,  Hui-Zhong ZHUANG ,  Lee-Chung LU ,  Li-Chun TIEN ,  Meng-Hung SHEN ,  Shang-Chih HSIEH ,  Chi-Yu LU

IPC分类号： G06F30/394 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/118

CPC分类号： G06F30/394 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11887

摘要： An integrated circuit includes a first power rail extending in a first direction, and configured to supply a first supply voltage, and a first region next to the first power rail. The first region includes a first conductive structure extending in the first direction, a first set of conductive structures extending in a second direction, and a first set of vias between the first set of conductive structures and the first conductive structure. The first set of conductive structures overlaps the first conductive structure and the first power rail, and is located on a second level. Each conductive structure of the first set of conductive structures is separated from each other in the first direction. Each via of the first set of vias is located where the first set of conductive structures overlaps the first conductive structure and couples the first set of conductive structures to the first conductive structure.