公开(公告)号：US20200295155A1

公开(公告)日：2020-09-17

申请号：US16890803

申请日：2020-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/02

Abstract: Semiconductor structures including active fin structures, dummy fin structures, epitaxy layers, a Ge containing oxide layer and methods of manufacture thereof are described. By implementing the Ge containing oxide layer on the surface of the epitaxy layers formed on the source/drain regions of some of the FinFET devices, a self-aligned epitaxy process is enabled. By implementing dummy fin structures and a self-aligned etch, both the epitaxy layers and metal gate structures from adjacent FinFET devices are isolated in a self-aligned manner.

公开(公告)号：US20200058556A1

公开(公告)日：2020-02-20

申请号：US16103704

申请日：2018-08-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Shi-Ning JU ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device includes a semiconductor substrate, a first fin structure and a second fin structure. The first fin structure includes a first fin and at least two first nano wires disposed above the first fin, and the first fin protrudes from the semiconductor substrate. The second fin structure includes a second fin and at least two second nano wires disposed above the second fin, and the second fin protrudes from the semiconductor substrate. Each first nano wire has a first width different from a second width of each second nano wire.

公开(公告)号：US20190165177A1

公开(公告)日：2019-05-30

申请号：US16176072

申请日：2018-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang CHEN ,  Chih-Ming LAI ,  Ching-Wei TSAI ,  Charles Chew-Yuen YOUNG ,  Jiann-Tyng TZENG ,  Kuo-Cheng CHING ,  Ru-Gun LIU ,  Wei-Hao WU ,  Yi-Hsiung LIN ,  Chia-Hao CHANG ,  Lei-Chun CHOU

IPC: H01L29/78 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L27/088

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US20190165127A1

公开(公告)日：2019-05-30

申请号：US15883684

申请日：2018-01-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Kuan-Lun CHENG ,  Chih-Hao WANG ,  Keng-Chu LIN ,  Shi-Ning JU

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234

Abstract: A semiconductor device is disclosed that includes a plurality of isolation regions. A fin is arranged between the plurality of isolation regions. One of the plurality of isolation regions includes a first atomic layer deposition (ALD) layer, a second ALD layer, a flowable chemical vapor deposition (FCVD) layer, and a third ALD layer. The first ALD layer includes a first trench. The second ALD layer is formed in the first trench of the first ALD layer. The FCVD layer is formed in the first trench of the first ALD layer and on the second ALD layer. The third ALD layer is formed on the FCVD layer.

公开(公告)号：US20190097056A1

公开(公告)日：2019-03-28

申请号：US16141509

申请日：2018-09-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Hao KUO ,  Jung-Hao CHANG ,  Chao-Hsien HUANG ,  Li-Te LIN ,  Kuo-Cheng CHING

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L21/84 ,  H01L21/306 ,  H01L21/02 ,  H01L27/12

Abstract: A device includes a semiconductor substrate, a first fin arranged over the semiconductor substrate, and an isolation structure. The first fin includes an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion. A top surface of the insulator layer is wider than a bottom surface of the upper portion of the first fin. The isolation structure surrounds the bottom portion of the first fin.

公开(公告)号：US20190096769A1

公开(公告)日：2019-03-28

申请号：US16204892

申请日：2018-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Chih-Hao Wang ,  Kuan-Lun Cheng ,  Yen-Ming Chen

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/02

Abstract: A method of forming a fin field effect transistor (finFET) on a substrate includes forming a fin structure on the substrate and forming a shallow trench isolation (STI) region on the substrate. First and second fin portions of the fin structure extend above a top surface of the STI region. The method further includes oxidizing the first fin portion to convert a first material of the first fin portion to a second material. The second material is different from the first material of the first fin portion and a material of the second fin portion. The method further includes forming an oxide layer on the oxidized first fin portion and the second fin portion and forming first and second polysilicon structures on the oxide layer.

公开(公告)号：US20190096765A1

公开(公告)日：2019-03-28

申请号：US15718740

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Chih-Hao WANG ,  Kuan-Lun CHENG

IPC: H01L21/8234 ,  H01L23/535 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L21/823418 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681

Abstract: The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.

公开(公告)号：US20190067448A1

公开(公告)日：2019-02-28

申请号：US15857196

申请日：2017-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Chih-Hao WANG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/45

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28114 ,  H01L21/3065 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a fin field effect transistors (finFET) on a substrate includes forming a fin structure on the substrate, forming a protective layer on the fin structure, and forming a polysilicon structure on the protective layer. The method further includes modifying the polysilicon structure such that a first horizontal dimension of a first portion of the modified polysilicon structure is smaller than a second horizontal dimension of a second portion of the modified polysilicon structure. The method further includes replacing the modified polysilicon structure with a gate structure having a first horizontal dimension of a first portion of the gate structure that is smaller than a second horizontal dimension of a second portion of the gate structure.

公开(公告)号：US20190027570A1

公开(公告)日：2019-01-24

申请号：US15653068

申请日：2017-07-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Chih-Hao WANG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/04 ,  H01L29/06 ,  H01L29/165

Abstract: In accordance with an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first cover layer is formed over the sacrificial gate structure, and a second cover layer is formed over the first cover layer. A source/drain epitaxial layer is formed. After the source/drain epitaxial layer is formed, the second cover layer is removed, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed. Part of the first semiconductor layers is removed in the gap, thereby forming spaces between the second semiconductor layers. The spaces are filled with a first insulating material.

公开(公告)号：US20170162695A1

公开(公告)日：2017-06-08

申请号：US15409014

申请日：2017-01-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Chih-Hao WANG ,  Ching-Wei TSAI ,  Wai-Yi LIEN

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02236 ,  H01L21/0228 ,  H01L21/02524 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02645 ,  H01L21/7624 ,  H01L29/0638 ,  H01L29/1604 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/401 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

Abstract: A method for manufacturing a semiconductor device includes forming a fin structure including a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. An isolation insulating layer is formed so that the channel layer of the fin structure protrudes from the isolation insulating layer and a part of or an entirety of the oxide layer is embedded in the isolation insulating layer. A gate structure is formed over the fin structure. A recessed portion is formed by etching a part of the fin structure not covered by the gate structure such that the oxide layer is exposed. A recess is formed in the exposed oxide layer. An epitaxial seed layer in the recess in the oxide layer. An epitaxial layer is formed in and above the recessed portion. The epitaxial layer is in contact with the epitaxial seed layer.