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公开(公告)号：US07812393B2
公开(公告)日：2010-10-12
申请号：US11982781
申请日：2007-11-05
IPC分类号： H01L23/62
CPC分类号： H01L29/0847 , H01L21/761 , H01L21/823462 , H01L21/823481 , H01L21/823493 , H01L21/8249 , H01L27/0623 , H01L27/088 , H01L27/098 , H01L29/0696 , H01L29/0878 , H01L29/0886 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/1087 , H01L29/402 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66106 , H01L29/66659 , H01L29/66704 , H01L29/66901 , H01L29/7825 , H01L29/7835 , H01L29/808 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.
摘要翻译： 所有低温工艺都用于制造不包括外延层的衬底中的各种半导体器件。 这些器件包括非隔离的横向DMOS，非隔离的扩展漏极或漂移的MOS器件，横沟DMOS，隔离的横向DMOS，JFET和耗尽型器件以及P-N二极管钳位和整流器和结终端。 由于该工艺消除了对高温处理的需要并采用“植入式”掺杂剂分布，所以它们构成了模块化结构，其允许将器件添加或省略到IC中，而无需改变用于产生剩余器件的工艺。
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公开(公告)号：US07738224B2
公开(公告)日：2010-06-15
申请号：US12286325
申请日：2008-09-30
IPC分类号： H02H9/00
CPC分类号： H01L29/735 , H01L27/0251 , H01L29/0626 , H01L29/0692 , H01L29/7317 , H01L29/7833 , H01L29/861 , H01L29/866
摘要： An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.
摘要翻译： 在半导体衬底的隔离区域中形成静电放电（ESD）保护器件。 ESD保护器件可以是MOS或双极晶体管或二极管的形式。 隔离结构可以包括深度植入的地板层和横向围绕隔离区域的一个或多个植入的孔。 隔离结构和ESD保护器件使用模块化工艺制造，其中几乎不包括热处理。 由于ESD器件是隔离的，所以两个或多个ESD器件可以彼此电“堆叠”，使得器件的触发电压相加在一起以实现更高的有效触发电压。
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公开(公告)号：US07737526B2
公开(公告)日：2010-06-15
申请号：US12002358
申请日：2007-12-17
IPC分类号： H01L29/00 , H01L21/76 , H01L21/331
CPC分类号： H01L21/823878 , H01L21/761 , H01L21/76224 , H01L21/823892 , H01L29/0649 , H01L29/0821 , H01L29/732 , H01L29/7371 , H01L2924/0002 , H01L2924/00
摘要： An isolation structure for a semiconductor device comprises a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate. A MOSFET is formed in the isolated pocket.
摘要翻译： 用于半导体器件的隔离结构包括地板隔离区域，位于地板隔离区域上方的电介质填充沟槽以及从沟槽底部向下延伸到地板隔离区域的侧壁隔离区域。 该结构在半导体衬底中提供了较深的隔离袋，同时限制了必须在衬底中被蚀刻的沟槽的深度。 在隔离的袋中形成MOSFET。
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公开(公告)号：US07719054B2
公开(公告)日：2010-05-18
申请号：US11443745
申请日：2006-05-31
IPC分类号： H01L23/62
CPC分类号： H01L29/0847 , H01L21/761 , H01L21/823462 , H01L21/823481 , H01L21/823493 , H01L21/8249 , H01L27/0623 , H01L27/088 , H01L27/098 , H01L29/0696 , H01L29/0878 , H01L29/0886 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/1087 , H01L29/402 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66106 , H01L29/66659 , H01L29/66704 , H01L29/66901 , H01L29/7825 , H01L29/7835 , H01L29/808 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.
摘要翻译： 所有低温工艺都用于制造不包括外延层的衬底中的各种半导体器件。 这些器件包括非隔离的横向DMOS，非隔离的扩展漏极或漂移的MOS器件，横沟DMOS，隔离的横向DMOS，JFET和耗尽型器件以及P-N二极管钳位和整流器和结终端。 由于该工艺消除了对高温处理的需要并采用“植入式”掺杂剂分布，所以它们构成了模块化结构，其允许将器件添加或省略到IC中，而无需改变用于产生剩余器件的工艺。
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公开(公告)号：US07626243B2
公开(公告)日：2009-12-01
申请号：US11499381
申请日：2006-08-04
IPC分类号： H01L29/861
CPC分类号： H01L29/735 , H01L27/0251 , H01L29/0626 , H01L29/0692 , H01L29/7317 , H01L29/7833 , H01L29/861 , H01L29/866
摘要： An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.
摘要翻译： 在半导体衬底的隔离区域中形成静电放电（ESD）保护器件。 ESD保护器件可以是MOS或双极晶体管或二极管的形式。 隔离结构可以包括深度植入的地板层和横向围绕隔离区域的一个或多个植入的孔。 隔离结构和ESD保护器件使用模块化工艺制造，其中几乎不包括热处理。 由于ESD器件是隔离的，所以两个或多个ESD器件可以彼此电“堆叠”，使得器件的触发电压相加在一起以实现更高的有效触发电压。
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公开(公告)号：US20090236683A1
公开(公告)日：2009-09-24
申请号：US12455212
申请日：2009-05-28
IPC分类号： H01L29/06
CPC分类号： H01L29/0646 , H01L21/26513 , H01L21/761 , H01L21/76224 , H01L21/76237 , H01L21/76243 , H01L21/76267 , H01L21/763 , H01L21/823481 , H01L21/823878 , H01L21/823892 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.
摘要翻译： 用于半导体衬底的各种隔离结构包括形成在衬底中的沟槽，其填充有电介质材料或填充有导电材料并且沿着沟槽的壁衬有介电层。 沟槽可以与掺杂的侧壁隔离区域组合使用。 沟槽和侧壁隔离区域都可以是环形的并且包围衬底的隔离袋。 隔离结构通过不包括显着的热处理或掺杂剂扩散的模块化注入和蚀刻工艺形成，使得所得到的结构是紧凑的并且可以紧密地堆积在衬底的表面中。
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公开(公告)号：US07576391B2
公开(公告)日：2009-08-18
申请号：US11982764
申请日：2007-11-05
IPC分类号： H01L27/108
CPC分类号： H01L29/0847 , H01L21/761 , H01L21/823462 , H01L21/823481 , H01L21/823493 , H01L21/8249 , H01L27/0623 , H01L27/088 , H01L27/098 , H01L29/0696 , H01L29/0878 , H01L29/0886 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/1087 , H01L29/402 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66106 , H01L29/66659 , H01L29/66704 , H01L29/66901 , H01L29/7825 , H01L29/7835 , H01L29/808 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.
摘要翻译： 所有低温工艺都用于制造不包括外延层的衬底中的各种半导体器件。 这些器件包括非隔离的横向DMOS，非隔离的扩展漏极或漂移的MOS器件，横沟DMOS，隔离的横向DMOS，JFET和耗尽型器件以及P-N二极管钳位和整流器和结终端。 由于该工艺消除了对高温处理的需要并采用“植入式”掺杂剂分布，所以它们构成了模块化结构，其允许将器件添加或省略到IC中，而无需改变用于产生剩余器件的工艺。
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公开(公告)号：US20080290450A1
公开(公告)日：2008-11-27
申请号：US12220986
申请日：2008-07-30
IPC分类号： H01L29/00
CPC分类号： H01L29/0646 , H01L21/26513 , H01L21/761 , H01L21/76224 , H01L21/76237 , H01L21/76243 , H01L21/76267 , H01L21/763 , H01L21/823481 , H01L21/823878 , H01L21/823892 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.
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公开(公告)号：US20150014810A1
公开(公告)日：2015-01-15
申请号：US14281075
申请日：2014-05-19
IPC分类号： H01L29/06
CPC分类号： H01L29/0646 , H01L21/26513 , H01L21/761 , H01L21/76224 , H01L21/76237 , H01L21/76243 , H01L21/76267 , H01L21/763 , H01L21/823481 , H01L21/823878 , H01L21/823892 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： Isolation structures for isolating semiconductor devices from a substrate include floor isolation regions buried within the substrate and one or more trenches extending from a surface of the substrate to the buried floor isolation region.
摘要翻译： 用于从衬底隔离半导体器件的隔离结构包括掩埋在衬底内的底部隔离区域和从衬底的表面延伸到掩埋地板隔离区域的一个或多个沟槽。
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公开(公告)号：US20050194643A1
公开(公告)日：2005-09-08
申请号：US11123448
申请日：2005-05-05
申请人： Richard Williams , Michael Cornell , Wai Tien Chan
发明人： Richard Williams , Michael Cornell , Wai Tien Chan
IPC分类号： H01L23/485 , H01L23/495 , H01L23/58 , H01L23/62 , H01L27/02 , H01L29/78
CPC分类号： H01L23/60 , H01L22/32 , H01L23/49562 , H01L23/62 , H01L24/05 , H01L24/48 , H01L24/49 , H01L27/0266 , H01L29/7802 , H01L29/7813 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05138 , H01L2224/05552 , H01L2224/05553 , H01L2224/05624 , H01L2224/05647 , H01L2224/0603 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/48091 , H01L2224/48247 , H01L2224/48463 , H01L2224/48464 , H01L2224/49111 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01039 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/12035 , H01L2924/12036 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , Y10S257/904 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection circuitry functional to protect the MOSFET. Before connecting the bonding pads together, the ESD protection circuitry and/or the MOSFET can be separately tested. A voltage higher than functioning ESD protection circuitry would permit can be used when testing the MOSFET. A packaging process such as wire bonding or attaching the die to a substrate in a flip-chip package can connect the bonding pads after testing.
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