公开(公告)号：US10229721B2

公开(公告)日：2019-03-12

申请号：US15586870

申请日：2017-05-04

申请人： Renesas Electronics Corporation

发明人： Koji Nii ,  Shigeki Ohbayashi ,  Yasumasa Tsukamoto ,  Makoto Yabuuchi

IPC分类号： G11C8/08 ,  G11C11/408 ,  G11C5/06 ,  G11C5/14 ,  G11C11/417 ,  G11C11/419

摘要： In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.

公开(公告)号：US10217751B2

公开(公告)日：2019-02-26

申请号：US16014920

申请日：2018-06-21

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Koji Nii ,  Makoto Yabuuchi ,  Yasumasa Tsukamoto ,  Kengo Masuda

IPC分类号： H01L27/088 ,  H01L27/11 ,  G11C11/412 ,  H01L29/10 ,  H01L29/66 ,  H01L21/265 ,  H01L27/02

摘要： In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region. The second halo region is set to have an impurity concentration higher than the impurity concentration of the first halo region. The third halo region is set to have an impurity concentration higher than the impurity concentration of the fourth halo region. The impurity concentration of the first halo region and the impurity concentration of the fourth halo region are different from each other.

公开(公告)号：US10153037B2

公开(公告)日：2018-12-11

申请号：US15885449

申请日：2018-01-31

申请人： Renesas Electronics Corporation

发明人： Yuichiro Ishii ,  Makoto Yabuuchi ,  Masao Morimoto

IPC分类号： G11C11/00 ,  G11C11/419 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/16 ,  G11C8/18 ,  G11C11/418 ,  G11C8/08 ,  G11C8/06

摘要： A circuit includes a memory cell array which includes: a plurality of memory cells; a plurality of word lines coupled to the memory cells, respectively, and a plurality of bit lines coupled to the memory cells, an address control circuit which includes: a first latch circuit into which a first address signal is input and from which a first output signal is output; a selection circuit into which a second address signal and the first output signal are input and which selects the first output signal or the second address signal for outputting the first output signal or the second address signal as a second output signal; a second latch circuit into which the second output signal is input and from which a third output signal is output; a decode circuit which decodes the third output signal and outputs a fourth output signal; and a word line drive circuit.

公开(公告)号：US20180350437A1

公开(公告)日：2018-12-06

申请号：US15926823

申请日：2018-03-20

申请人： Renesas Electronics Corporation

发明人： Yohei Sawada ,  Makoto Yabuuchi ,  Masao Morimoto

IPC分类号： G11C15/04

CPC分类号： G11C15/04

摘要： A content addressable memory includes a plurality of TCAM cells which configure one entry, a first word line coupled to the TCAM cells, a second word line coupled to the TCAM cells and a match line coupled to the TCAM cells and further includes a valid cell which stores a valid bit which indicates validity or invalidity of the entry, a bit line coupled to the valid line and a selection circuit which is coupled to the first word line and the second word line and sets the valid cell to a selected state in accordance with a situation where the first word line or the second word line is set to the selected state.

公开(公告)号：US09978445B2

公开(公告)日：2018-05-22

申请号：US15373783

申请日：2016-12-09

申请人： Renesas Electronics Corporation

发明人： Toshiaki Sano ,  Ken Shibata ,  Shinji Tanaka ,  Makoto Yabuuchi ,  Noriaki Maeda

IPC分类号： G11C7/00 ,  G11C11/419 ,  G11C7/12 ,  G11C11/418 ,  G11C8/16 ,  G11C11/412

CPC分类号： G11C11/419 ,  G11C7/12 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418

摘要： A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

公开(公告)号：US09922703B2

公开(公告)日：2018-03-20

申请号：US15481345

申请日：2017-04-06

申请人： Renesas Electronics Corporation

发明人： Yuichiro Ishii ,  Makoto Yabuuchi ,  Masao Morimoto

IPC分类号： G11C11/00 ,  G11C11/419 ,  G11C11/418 ,  G11C8/16 ,  G11C7/22 ,  G11C7/10 ,  G11C8/00 ,  G11C8/18 ,  G11C7/00

CPC分类号： G11C11/419 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C7/222 ,  G11C8/00 ,  G11C8/06 ,  G11C8/08 ,  G11C8/16 ,  G11C8/18 ,  G11C11/418

摘要： A multiport memory includes an address control circuit, a memory array, a data input-output circuit and a control circuit and first and second address signals and a clock signal are input through two ports. The address control circuit includes first and second latch circuits, a selection circuit, a decode circuit and a word line drive circuit. The first address signal input through one port is input into the first latch circuit and the second address signal input through the other port is input into the selection circuit. The selection circuit selects one of the first and second address signals, the second latch circuit latches and outputs the selected address signal to the decode circuit. The word line drive circuit drives a word line on the basis of an output signal from the decode circuit.

公开(公告)号：US09830977B2

公开(公告)日：2017-11-28

申请号：US15239410

申请日：2016-08-17

申请人： Renesas Electronics Corporation

发明人： Makoto Yabuuchi ,  Hidehiro Fujiwara

IPC分类号： G11C5/14 ,  G11C11/419 ,  G11C11/417 ,  G11C11/418 ,  G11C17/12

CPC分类号： G11C11/419 ,  G11C11/417 ,  G11C11/418 ,  G11C17/12

摘要： There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.

公开(公告)号：US20170277455A1

公开(公告)日：2017-09-28

申请号：US15418389

申请日：2017-01-27

申请人： Renesas Electronics Corporation

发明人： Takeshi Sunada ,  Daisuke Oshida ,  Makoto Yabuuchi

IPC分类号： G06F3/06 ,  G11C29/44 ,  G11C29/12 ,  G06F11/30 ,  G06F11/34

CPC分类号： G11C29/44 ,  G06F11/008 ,  G06F11/2284 ,  G06F11/3072 ,  G06F2201/81 ,  G11C16/349 ,  G11C17/18 ,  G11C29/12005 ,  G11C29/42 ,  G11C29/50004 ,  G11C29/52 ,  G11C2029/0409

摘要： The disclosed invention can provide a semiconductor device, a lifetime prediction system, and a lifetime prediction method enabling it to notify a user that a semiconductor device is likely to become faulty, before the semiconductor device becomes faulty. A semiconductor device includes functional units and a lifetime prediction circuit. The lifetime prediction circuit acquires a deterioration degree indicating a degree of how each functional unit deteriorates, using a signal that is output from each functional unit. The lifetime prediction circuit executes processing to make a notification that the semiconductor device is close to its lifetime, if the deterioration degree is more than a first threshold.

公开(公告)号：US09721648B2

公开(公告)日：2017-08-01

申请号：US15214253

申请日：2016-07-19

申请人： Renesas Electronics Corporation

发明人： Makoto Yabuuchi

IPC分类号： G11C11/00 ,  G11C11/419

CPC分类号： G11C11/419

摘要： There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.

公开(公告)号：US09697911B2

公开(公告)日：2017-07-04

申请号：US15337139

申请日：2016-10-28

申请人： Renesas Electronics Corporation

发明人： Makoto Yabuuchi

IPC分类号： G11C7/22 ,  G11C29/12 ,  G11C8/08 ,  G11C7/12 ,  H01L27/11

CPC分类号： G11C29/1201 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C8/08 ,  G11C11/412 ,  G11C11/419 ,  G11C29/12015 ,  G11C2029/1202 ,  G11C2029/1204 ,  H01L27/1104 ,  H01L27/1116

摘要： Provided is a semiconductor storage device including: first memory cells; first word lines; first bit lines; a first common bit line; second memory cells; second word lines; second bit lines; a second common bit line; a first selection circuit that connects the first common bit line to a first bit line selected from the first bit lines; a second selection circuit that connects the second common bit line to a second bit line selected from the second bit lines; a word line driver that activates any one of the first and second word lines; a reference current supply unit that supplies a reference current to a common bit line among the first and second common bit lines, the common bit line not being electrically connected to a data read target memory cell; and a sense amplifier that amplifies a potential difference between the first and second common bit lines.