Abstract:
A transistor cell includes a drift region, a source region, and a body region arranged between the source region and the drift region in a semiconductor body. A drain region is below the drift region. An insulated gate trench extends into the drift region. A diode region extends deeper into the drift region than the insulated gate trench and partly under the insulated gate trench so as to form a pn junction with the drift region below a bottom of the insulated gate trench. The body region adjoins a first sidewall of the insulated gate trench and the diode region adjoins a second sidewall of the insulated gate trench opposite the first sidewall so that the body region of the transistor cell and a channel region including a region of the body region extending along the first sidewall are separated from the diode region by the insulated gate trench.
Abstract:
A semiconductor device includes a semiconductor body and a device cell in the semiconductor body. The device cell includes: drift, source, body and diode regions; a pn junction between the diode and drift regions; a trench with first and second opposing sidewalls and a bottom, the body region adjoining the first sidewall, the diode region adjoining the second sidewall, and the pn junction adjoining the trench bottom; a gate electrode in the trench and dielectrically insulated from the source, body, diode and drift regions by a gate dielectric; a further trench extending from a first surface of the semiconductor body into the semiconductor body; a source electrode arranged in the further trench adjoining the source and diode regions. The diode region includes a lower diode region arranged below the trench bottom. The lower diode region has a maximum of a doping concentration distant to the trench bottom.
Abstract:
A semiconductor device includes a semiconductor body and at least one device cell integrated in the semiconductor body. Each device cell includes: a drift region, a source region, and a body region arranged between the source and drift regions; a diode region and a pn junction between the diode and drift regions; a trench having a first sidewall, a second sidewall opposite the first sidewall, and a bottom, the body region adjoining the first sidewall, the diode region adjoining the second sidewall, and the pn junction adjoining the bottom; a gate electrode in the trench and dielectrically insulated from the body, diode and drift regions by a gate dielectric. The diode region has a lower diode region arranged below the trench bottom, and the lower diode region has a maximum of a doping concentration distant to the trench bottom. A corresponding method of manufacturing the device also is provided.
Abstract:
A method includes providing a silicon carbide substrate, wherein a gate trench extends from a main surface of the silicon carbide substrate into the silicon carbide substrate and wherein a gate dielectric is formed on at least one sidewall of the gate trench, and forming a gate electrode in the gate trench, the gate electrode including a metal structure and a semiconductor layer between the metal structure and the gate dielectric.
Abstract:
A method of manufacturing semiconductor devices includes: forming source regions of a first conductivity type in a SiC-based semiconductor substrate, wherein dopants are introduced selectively through first segments of first mask openings in a first dopant mask and wherein a longitudinal axis of the first mask opening extends into a first horizontal direction; forming pinning regions of a complementary second conductivity type, wherein dopants are selectively introduced through second segments of the first mask openings and wherein the first and second segments alternate along the first horizontal direction; and forming body regions of the second conductivity type, wherein dopants are selectively introduced through second mask openings in a second dopant mask, wherein a width of the second mask openings along a second horizontal direction orthogonal to the first horizontal direction is greater than a width of the first mask openings.
Abstract:
A semiconductor device includes trench gate structures that extend from a first surface into a semiconductor body of silicon carbide. The trench gate structures include a gate electrode and are spaced apart from one another along a first horizontal direction and extend into a body region with a longitudinal axis parallel to the first horizontal direction. First sections of first pn junctions between the body regions and a drift structure are tilted to the first surface and parallel to the first horizontal direction. Source regions form second pn junctions with the body regions. A gate length of the gate electrode along a second horizontal direction orthogonal to the first horizontal direction is greater than a channel length between the first sections of the first pn junctions and the second pn junctions.
Abstract:
A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.
Abstract:
By using at least one of a processor device and model transistor cells, a set of design parameters for at least one of a transistor cell and a drift structure of a wide band-gap semiconductor device is determined, wherein an on state failure-in-time rate and an off state failure-in-time rate of a gate dielectric of the transistor cell are within a same order of magnitude for a predefined on-state gate-to-source voltage, a predefined off-state gate-to-source voltage, and a predefined off-state drain-to-source voltage.
Abstract:
According to an embodiment of a semiconductor device, the device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. Rows of source regions of a first conductivity type are formed in the SiC substrate and extend lengthwise in parallel in a second direction which is transverse to the first direction. Rows of body regions of a second conductivity type opposite the first conductivity type are formed in the SiC substrate below the rows of source regions. Rows of body contact regions of the second conductivity type are formed in the SiC substrate. The rows of body contact regions extend lengthwise in parallel in the second direction. First shielding regions of the second conductivity type are formed deeper in the SiC substrate than the rows of body regions.
Abstract:
A semiconductor device includes a semiconductor body and at least one device cell integrated in the semiconductor body. Each device cell includes a drift region, a source region, and a body region arranged between the source region and the drift region. A gate trench extends from a first surface of the semiconductor body, through the source and body regions and into the drift region. A diode region extends under the gate trench. A pn junction is formed between the diode and drift regions below the gate trench. A gate electrode arranged in the gate trench is dielectrically insulated from the source, body, diode and drift regions by a gate dielectric. A contact trench spaced apart from the gate trench extends from the first surface into the source region. A source electrode arranged in the contact trench adjoins the source region at a sidewall of the contact trench.