公开(公告)号：US20210296178A1

公开(公告)日：2021-09-23

申请号：US16823876

申请日：2020-03-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Su Chen Fan ,  Heng Wu ,  Julien Frougier

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

Abstract: A method for fabricating a semiconductor device includes forming top source/drain contact material on top source/drain material disposed on one or more fins of a base structure, and subtractively patterning the top source/drain contact material to form at least one top source/drain contact. The at least one top source/drain contact has a positive tapered geometry. The method further includes cutting exposed end portions of the top source/drain material to form at least one top source/drain region underneath the at least one top source/drain contact.

公开(公告)号：US20210280776A1

公开(公告)日：2021-09-09

申请号：US16809916

申请日：2020-03-05

Applicant: International Business Machines Corporation

Inventor： Julien Frougier ,  Ruilong Xie ,  Alexander Reznicek ,  Bruce B. Doris

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: An embedded magnetoresistive random-access memory (MRAM) device including a portion of a metal wiring layer above a semiconductor device and a bottom electrode over the portion of the metal wiring layer. The embedded MRAM where the bottom electrode connects to a first portion of a bottom surface of a magnetoresistive random access memory pillar and a sidewall spacer is on the magnetoresistive random access memory pillar. The embedded MRAM device includes a ring of inner metal is on the portion of the metal wiring layer surrounding a portion of the bottom electrode.

公开(公告)号：US11094784B2

公开(公告)日：2021-08-17

申请号：US16377815

申请日：2019-04-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Julien Frougier ,  Chanro Park ,  Tenko Yamashita

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/16 ,  H01L29/786

Abstract: A method of fabricating a semiconductor device is described. The method includes forming a stack of sacrificial layers on a substrate. A U-shaped trench is formed in the stack of the sacrificial layers. A first U-shaped channel layer is deposited in the U-shaped trench. A first U-shaped sacrificial layer is conformally formed covering the U-shaped channel layer. A second U-shaped channel layer is conformally deposited covering the first U-shaped sacrificial layer. A gate is formed around the first and the second U-shaped channel layers.

公开(公告)号：US11011638B2

公开(公告)日：2021-05-18

申请号：US16550793

申请日：2019-08-26

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Julien Frougier ,  Kangguo Cheng ,  Chanro Park

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/41 ,  H01L29/66 ,  H01L29/49 ,  H01L29/417

Abstract: An integrated semiconductor device having a gate structure adjacent to a semiconductor body at a channel region, the channel region being positioned laterally between source/drain regions. Metal plugs are on the source/drain regions, and rectangular-shaped or trapezoidal-shaped plug caps are above and immediately adjacent to the metal plugs. A self-aligned metal filled contact (CA) is conductively coupled to one of the metal plugs on the source and drain regions, and a self-aligned metal filled contact (CBoA) is conductively coupled to the gate structure. The device further includes a low k dielectric layer that includes a continuous airgap having an inverted u-shape formed about the gate structure and breaks at about a portion of the gate structure including the self-aligned metal filled contact (CBoA). Also, methods for forming the device including the uniquely shaped continuous airgap are disclosed.

公开(公告)号：US20200321434A1

公开(公告)日：2020-10-08

申请号：US16377815

申请日：2019-04-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Julien Frougier ,  Chanro Park ,  TENKO YAMASHITA

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L27/088

Abstract: A method of fabricating a semiconductor device is described. The method includes forming a stack of sacrificial layers on a substrate. A U-shaped trench is formed in the stack of the sacrificial layers. A first U-shaped channel layer is deposited in the U-shaped trench. A first U-shaped sacrificial layer is conformally formed covering the U-shaped channel layer. A second U-shaped channel layer is conformally deposited covering the first U-shaped sacrificial layer. A gate is formed around the first and the second U-shaped channel layers.

公开(公告)号：US20200273979A1

公开(公告)日：2020-08-27

申请号：US16286731

申请日：2019-02-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： RUILONG XIE ,  Julien Frougier ,  CHANRO PARK ,  Edward Nowak ,  Yi Qi ,  Kangguo Cheng ,  NICOLAS LOUBET

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/324 ,  H01L27/088

Abstract: Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack can include one or more first semiconductor layers and one or more first sacrificial layers. A trench is formed by removing a portion of the one or more first semiconductor layers and the one or more first sacrificial layers. The trench exposes a surface of a bottommost sacrificial layer of the one or more first sacrificial layers. The trench can be filled with one or more second semiconductor layers and one or more second sacrificial layers such that each of the one or more second semiconductor layers is in contact with a sidewall of one of the one or more first semiconductor layers.

公开(公告)号：US20200044057A1

公开(公告)日：2020-02-06

申请号：US16597428

申请日：2019-10-09

Applicant: International Business Machines Corporation

Inventor： Julien Frougier ,  Ruilong Xie ,  Steven Bentley ,  Kangguo Cheng ,  NICOLAS LOUBET ,  PIETRO MONTANINI

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78

Abstract: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.

公开(公告)号：US20190386113A1

公开(公告)日：2019-12-19

申请号：US16009196

申请日：2018-06-14

Applicant: International Business Machines Corporation

Inventor： Nicolas Loubet ,  Julien Frougier ,  Wenyu Xu ,  Zhenxing Bi

IPC: H01L29/66 ,  H01L29/775 ,  H01L21/311

Abstract: A semiconductor device is described. The semiconductor device includes a nanosheet stack including a sacrificial nanosheet oriented substantially parallelly to a substrate and a channel nanosheet disposed on the sacrificial nanosheet. The semiconductor device includes a gate formed in a direction orthogonal to the plane of the nanosheet stack, with a gate spacer positioned along a sidewall of the gate. The semiconductor device includes an inner spacer liner deposited around the nanosheet stack and the gate spacer. A first etching of the inner spacer liner is configured to produce an outer profile of the inner spacer liner, the outer profile having a substantially flat side section relative to an edge of the channel nanosheet. A second etching of the inner spacer liner is configured to remove substantially all material of the inner spacer liner from the edge of the channel nanosheet.

公开(公告)号：US20190259856A1

公开(公告)日：2019-08-22

申请号：US15898314

申请日：2018-02-16

Applicant: International Business Machines Corporation

Inventor： Julien Frougier ,  Ruilong Xie ,  Steven Bentley ,  Kangguo Cheng ,  Nicolas Loubet ,  Pietro Montanini

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78

Abstract: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.

公开(公告)号：US20190252465A1

公开(公告)日：2019-08-15

申请号：US15894108

申请日：2018-02-12

Applicant: International Business Machines Corporation

Inventor： Julien Frougier ,  Nicolas Loubet ,  Ruilong Xie ,  Daniel Chanemougame ,  Ali Razavieh ,  Kangguo Cheng

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L21/32139 ,  H01L29/785 ,  H01L45/1683

Abstract: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, and a trench extending to the source/drain. A trench contact is formed in the trench in contact with the source/drain. A recess is formed in a portion of the trench contact below a top surface of the cap using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the trench contact. A source/drain contact is formed upon the BRS material, a portion of the trench contact, the BRS material, and a portion of the source/drain contact forming a reversible switch.