公开(公告)号：US20090039999A1

公开(公告)日：2009-02-12

申请号：US12186317

申请日：2008-08-05

申请人： Tomoharu Fujii ,  Masahiro Sunohara ,  Manabu Nakamura

发明人： Tomoharu Fujii ,  Masahiro Sunohara ,  Manabu Nakamura

IPC分类号： H01F5/00

CPC分类号： H01F17/0006 ,  H01F27/323 ,  H01F41/041 ,  H01F41/122 ,  H01F2017/0046 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/645 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2924/19105 ,  H01L2924/3011 ,  Y10T29/4902

摘要： An inductor device formed on a semiconductor substrate includes an inductor body penetrating the semiconductor substrate, taking a spiral shape and having a conductivity, and an insulating film provided between a side surface of the inductor body and the semiconductor substrate.

摘要翻译： 形成在半导体衬底上的电感器件包括穿过半导体衬底的电感体，呈螺旋形并具有导电性，以及设置在电感体侧面和半导体衬底之间的绝缘膜。

公开(公告)号：US20080153286A1

公开(公告)日：2008-06-26

申请号：US12028924

申请日：2008-02-11

申请人： Masahiro SUNOHARA ,  Mitsutoshi HIGASHI

发明人： Masahiro SUNOHARA ,  Mitsutoshi HIGASHI

IPC分类号： H01L21/768

CPC分类号： H01L24/12 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05576 ,  H01L2224/05624 ,  H01L2224/1134 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor chip includes a semiconductor substrate having a first principal surface, and having a device layer on the first principal surface in which a semiconductor device is formed, an electrode pad disposed on the first principal surface of the semiconductor substrate and electrically connected to the semiconductor device, a through via formed in a through hole penetrating through the semiconductor substrate and the electrode pad, and an Au bump deposited on the electrode pad and the through via such as to electrically connect between the electrode pad and the through via.

摘要翻译： 半导体芯片包括具有第一主表面的半导体衬底，并且在形成有半导体器件的第一主表面上具有器件层，设置在半导体衬底的第一主表面上并电连接到半导体的电极焊盘 器件，穿过贯穿半导体衬底和电极焊盘的通孔中形成的通孔，以及沉积在电极焊盘和通孔上的Au凸块，以电连接电极焊盘和通孔。

公开(公告)号：US20080150109A1

公开(公告)日：2008-06-26

申请号：US11962232

申请日：2007-12-21

申请人： Masahiro Sunohara ,  Akinori Shiraishi ,  Kei Murayama ,  Yuichi Taguchi ,  Naoyuki Koizumi ,  Mitsutoshi Higashi

发明人： Masahiro Sunohara ,  Akinori Shiraishi ,  Kei Murayama ,  Yuichi Taguchi ,  Naoyuki Koizumi ,  Mitsutoshi Higashi

IPC分类号： H01L23/46

CPC分类号： H01L23/427 ,  H01L23/473 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/0401

摘要： An electronic component has a substrate made of silicon in which a flow path for circulating a refrigerant is formed, a conductive pattern formed on a first principal surface of the substrate, a via plug penetrating the substrate and also connected to the conductive pattern, and an elastically deformable external connection terminal installed on a second principal surface of the substrate.

摘要翻译： 电子部件具有由硅构成的基板，其中形成有用于使制冷剂循环的流路，形成在基板的第一主表面上的导电图案，穿透基板的通孔塞，并且还连接到导电图案， 可弹性变形的外部连接端子安装在基板的第二主表面上。

公开(公告)号：US20080012120A1

公开(公告)日：2008-01-17

申请号：US11826263

申请日：2007-07-13

申请人： Masahiro Sunohara

发明人： Masahiro Sunohara

IPC分类号： H01L23/04 ,  H01L21/4763

CPC分类号： H05K3/467 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2924/0002 ,  H05K3/28 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/09518 ,  H05K2203/1338 ,  H01L2924/00

摘要： A multilayer wiring substrate has a plurality of wiring layers and interlayer insulating films, as well as a via of a type which connects between adjacent wiring layers and a via of a type which connects upper and lower wiring layers through two or more interlayer insulating films, wherein at least some of the interlayer insulating films are formed of inorganic insulating films, and the via of the type, which connects upper and lower wiring layers through two or more interlayer insulating films, is formed as a single via which penetrates through the interlayer insulating films all of which are formed of the inorganic insulating films. Preferably, all of the insulating films are formed of the inorganic insulating films, and the inorganic insulating films are formed by a low-temperature CVD method. The thickness of the inorganic insulating films is preferably between 0.5 and 2.0 μm.

摘要翻译： 多层布线基板具有多个布线层和层间绝缘膜，以及连接相邻布线层的类型的通孔和通过两层或更多层间绝缘膜连接上下布线层的通孔， 其中层间绝缘膜中的至少一些由无机绝缘膜形成，并且通过两层或更多层间绝缘膜连接上和下布线层的类型的通孔形成为穿过层间绝缘体的单个通孔 所有这些膜都是由无机绝缘膜形成的。 优选地，所有绝缘膜由无机绝缘膜形成，并且通过低温CVD方法形成无机绝缘膜。 无机绝缘膜的厚度优选为0.5〜2.0μm。

公开(公告)号：US20070290329A1

公开(公告)日：2007-12-20

申请号：US11812149

申请日：2007-06-15

申请人： Kei Murayama ,  Mitsutoshi Higashi ,  Naoyuki Koizumi ,  Yuichi Taguchi ,  Akinori Shiraishi ,  Masahiro Sunohara

发明人： Kei Murayama ,  Mitsutoshi Higashi ,  Naoyuki Koizumi ,  Yuichi Taguchi ,  Akinori Shiraishi ,  Masahiro Sunohara

IPC分类号： H01L23/12

CPC分类号： H01L25/167 ,  H01L23/147 ,  H01L23/4926 ,  H01L23/62 ,  H01L24/48 ,  H01L25/16 ,  H01L2224/32145 ,  H01L2224/48137 ,  H01L2224/4823 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12035 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In a semiconductor device 100, a light emitting element 120 has been mounted on an upper plane of a semiconductor substrate 102. In an impurity diffusion region of the semiconductor substrate 102, a P conducting type of a layer 104, and an N layer 106 have been formed, while an N conducting type impurity is implanted to the P layer 104, and then the implanted impurity is diffused to constitute the N layer 106. A zener diode 108 made of a semiconductor device has been formed by the P layer 104 and the N layer 106.

摘要翻译： 在半导体器件100中，发光元件120已经被安装在半导体衬底102的上平面上。在半导体衬底102的杂质扩散区域中，P导电类型的层104和N层106具有 形成N导电型杂质，然后将N导电型杂质注入到P层104中，然后将注入的杂质扩散以构成N层106.由P层104形成由半导体器件制成的齐纳二极管108， N层106。

公开(公告)号：US07198986B2

公开(公告)日：2007-04-03

申请号：US11049958

申请日：2005-02-04

申请人： Masahiro Sunohara

发明人： Masahiro Sunohara

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L24/24 ,  H01L21/563 ,  H01L24/82 ,  H01L25/0657 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/92 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： An electronic parts built-in substrate of the present invention includes a wiring substrate having connecting pads, a first electronic parts a bump of which is flip-chip connected to the connecting pad, a second electronic parts having a larger area than an area of the first electronic parts a bump of which is flip-chip connected to the connecting pad arranged on an outside of a periphery of the first electronic parts and which is packaged at a predetermined interval over the first electronic parts, and a filling insulating body filled in a clearance between the first electronic parts and the wiring substrate and clearances between the second electronic parts and the first electronic parts and the wiring substrate, wherein the first electronic parts is buried in the filling insulating body.

摘要翻译： 本发明的电子部件内置基板包括具有连接焊盘的布线基板，其凸块与连接焊盘倒装连接的第一电子部件，具有比所述连接焊盘的面积大的面积的第二电子部件 第一电子部件，其凸起倒装芯片连接到布置在第一电子部件的周边的外侧上的连接焊盘，并且以预定间隔被封装在第一电子部件上，以及填充绝缘体， 第一电子部件和布线基板之间的间隙以及第二电子部件与第一电子部件和布线基板之间的间隙，其中第一电子部件被埋在填充绝缘体中。

公开(公告)号：US07195988B2

公开(公告)日：2007-03-27

申请号：US10751657

申请日：2004-01-06

申请人： Yoshihiko Nemoto ,  Masahiro Sunohara ,  Kenji Takahashi

发明人： Yoshihiko Nemoto ,  Masahiro Sunohara ,  Kenji Takahashi

IPC分类号： H01L21/46 ,  H01L21/30

CPC分类号： H01L21/6835 ,  H01L21/3043 ,  H01L21/6836 ,  H01L21/78 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  Y10S438/977

摘要： A conveyance system for a semiconductor wafer can be used without any change before and after a support plate is adhered to the wafer. Also, the finish accuracy of the wafer and the positioning accuracy between the wafer and the support plate can be relaxed, thus improving the manufacturing efficiency. The wafer is formed on its peripheral portion with a stepped portion, which is deeper than a finished thickness obtained by partial removal of the rear surface thereof and which can be eliminated by the partial removal of the wafer rear surface. The separation portion has a length which extends radially outward from a flat surface, and which is greater than a total sum of a maximum-minimum difference between the finish allowances of the diameters of the wafer and the support plate, and a maximum value of a positioning error between the wafer and the support plate generated upon adhesion thereof.

摘要翻译： 在支撑板粘附到晶片之前和之后，可以不用改变地使用半导体晶片的输送系统。 此外，晶片的精加工精度和晶片与支撑板之间的定位精度可以被放宽，从而提高制造效率。 晶片在其周边部分上形成有阶梯部分，其比通过部分去除其后表面获得的成品厚度更深，并且可以通过部分去除晶片后表面而消除晶片。 分离部分具有从平坦表面径向向外延伸的长度，并且其长度大于晶片和支撑板的直径的精加工余量之间的最大 - 最小差值的总和以及最大值 在粘合时产生的晶片和支撑板之间的定位误差。

公开(公告)号：US07183647B2

公开(公告)日：2007-02-27

申请号：US10709096

申请日：2004-04-13

申请人： Kei Murayama ,  Masahiro Sunohara

发明人： Kei Murayama ,  Masahiro Sunohara

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L23/562 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/81206 ,  H01L2224/81801 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H05K1/113 ,  H05K3/328 ,  H05K2201/09436 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2201/10674 ,  H05K2203/0285 ,  H01L2924/00

摘要： In a wiring substrate of the present invention in which a bump of an electronic parts is bonded to a connection pad of a wiring pattern provided on an insulating film by an ultrasonic flip-chip packaging, a via hole into which a via post acting as a strut to support the connection pad upon the ultrasonic flip-chip packaging is filled is arranged in the insulating film under the connection pad.

摘要翻译： 在本发明的布线基板中，电子部件的凸块通过超声波倒装芯片封装被接合到设置在绝缘膜上的布线图案的连接焊盘，通孔，通孔作为 在超声波倒装芯片封装被填充的支撑件支撑连接垫被布置在连接垫下面的绝缘膜中。

公开(公告)号：US20070029654A1

公开(公告)日：2007-02-08

申请号：US11485397

申请日：2006-07-13

申请人： Masahiro Sunohara ,  Mitsutoshi Higashi ,  Akinori Shiraishi

发明人： Masahiro Sunohara ,  Mitsutoshi Higashi ,  Akinori Shiraishi

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/12 ,  H01L23/04 ,  H01L29/84

CPC分类号： B81C1/00301 ,  B81B2207/096 ,  B81C2203/0109 ,  H01L23/055 ,  H01L23/147 ,  H01L27/14618 ,  H01L2224/16225 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/16251 ,  H01L2924/00

摘要： In an electronic parts packaging structure of the present invention, an electronic parts is mounted or formed on a silicon circuit substrate having a structure in which wiring layers on both sides thereof are connected to each other through a through electrode, and a protruded bonding portion which is ring-shaped and is made of glass, of a seal cap having a structure in which a cavity is constituted by the protruded bonding portion, is anodically bonded to a bonding portion of the silicon circuit substrate, thus, the electronic parts is hermetically sealed in the cavity of the sealing cap.

摘要翻译： 在本发明的电子零件封装结构中，电子部件安装或形成在具有通过贯通电极彼此连接的两侧的布线层的结构的硅电路基板上，突出的接合部 环状，由玻璃制成，具有由突出接合部构成空腔的结构的密封盖阳极结合到硅电路基板的接合部，因此电子部件被密封 在密封盖的空腔中。

公开(公告)号：US07134195B2

公开(公告)日：2006-11-14

申请号：US10796004

申请日：2004-03-10

申请人： Masahiro Sunohara ,  Kei Murayama ,  Mitsutoshi Higashi

发明人： Masahiro Sunohara ,  Kei Murayama ,  Mitsutoshi Higashi

IPC分类号： H05K3/30 ,  H05K3/02 ,  H05K3/10

CPC分类号： H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/24 ,  H01L23/5389 ,  H01L24/27 ,  H01L24/29 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16195 ,  H05K1/185 ,  H05K3/4644 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  H01L2924/00

摘要： A method of production of a multilayer circuit board comprised of a multilayer structure circuit formed by a plurality of interconnect layers and insulation layers stacked together and a semiconductor chip included therein, including the steps of placing a semiconductor chip having a polished back surface, with its active surface facing downward, on an already formed lower interconnect layer and forming an insulation layer over the layer on which the semiconductor chip has been placed, the method further including the step of treating the polished back surface of the semiconductor chip to improve its bondability with the insulation layer before the step for formation of the insulation layer.

摘要翻译： 一种制造多层电路板的方法，包括由多个互连层和堆叠在一起的绝缘层形成的多层结构电路和包括在其中的半导体芯片，包括以下步骤：将具有抛光后表面的半导体芯片放置在其中 活性表面朝下，在已经形成的下互连层上，并且在其上放置半导体芯片的层上形成绝缘层，该方法还包括处理半导体芯片的抛光后表面以提高其与 绝缘层前后形成绝缘层。