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公开(公告)号：US20130271192A1
公开(公告)日：2013-10-17
申请号：US13850500
申请日：2013-03-26
发明人： Peter Vlasenko , Dieter Haerle
IPC分类号： H03L7/081
CPC分类号： H03L7/081 , H03L7/0814 , H03L7/0818 , H03L7/0891 , H03L7/095 , H03L7/10
摘要： A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.
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62.发明申请公开(公告)号：US20130119542A1
公开(公告)日：2013-05-16
申请号：US13675163
申请日：2012-11-13
发明人： HakJune OH
IPC分类号： H01L23/498
CPC分类号： H01L25/0657 , H01L23/49816 , H01L24/73 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06562 , H01L2924/15192 , H01L2924/15311 , H01L2924/00012 , H01L2224/32145 , H01L2924/00 , H01L2924/00014
摘要： A multi-chip package has a substrate, and a plurality of memory dies stacked on the substrate. A plurality of buffer dies each has an input and an output. The input of a first buffer die is connectable to an external input. The output of a last buffer die of the plurality of buffer dies is connectable to an external output. Each of the remaining inputs and outputs is connected respectively to an output or an input of another of the plurality of buffer dies to form a serial connection between the plurality of buffer dies. Each of the memory dies is connected to one of the buffer dies, such that each buffer die is connected to its respective memory dies in parallel arrangement. A memory device having multiple serially interconnected MCPs and a controller is also described.
摘要翻译： 多芯片封装具有基板和堆叠在基板上的多个存储器管芯。 多个缓冲模具各自具有输入和输出。 第一缓冲管芯的输入可连接到外部输入端。 多个缓冲管芯的最后一个缓冲管芯的输出可连接到外部输出。 每个剩余的输入和输出分别连接到多个缓冲管芯中另一个的输出端或输入端，以形成多个缓冲管芯之间的串联连接。 每个存储器管芯连接到缓冲管芯之一，使得每个缓冲管芯以并联布置连接到其各自的存储器管芯。 还描述了具有多个串行互连的MCP和控制器的存储器件。
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63.发明申请DISTRIBUTED NETWORK MANAGEMENT HIERARCHY IN A MULTI-STATION COMMUNICATION NETWORK 有权分布式网络管理在多站通信网络中的分层公开(公告)号：US20130117828A1
公开(公告)日：2013-05-09
申请号：US13724022
申请日：2012-12-21
发明人： James David Larsen
IPC分类号： H04L29/06
CPC分类号： H04L63/08 , H04L41/0213 , H04L41/12 , H04L63/10 , H04L63/20
摘要： The invention relates to a network and to a method of operating a network. The network comprises a plurality of stations each able to transmit and receive data so that the network can transmit data between stations via at least one selected intermediate station. The network further comprises a plurality of levels of stations including a first level comprising user and/or seed stations, a second level comprising auxiliary stations providing access to auxiliary networks, a third level comprising at least one location management station, and a fourth level comprising at least one authentication station. The method comprises transmitting, from or on behalf of a station on the first level requiring authentication, to an authentication station via one or more stations, an authentication request message. In response, the authentication station transmits authentication data to authenticate the station on the first level.
摘要翻译： 本发明涉及网络和操作网络的方法。 网络包括多个站，每个站能够发送和接收数据，使得网络可以经由至少一个所选择的中间站在站点之间传送数据。 网络还包括多个级别的站，包括包括用户和/或种子站的第一级，第二级包括提供对辅助网络的访问的辅助站，包括至少一个位置管理站的第三层，以及包括 至少一个认证台。 所述方法包括：通过一个或多个站向认证站发送来自或代表要求认证的第一级的站，或者向其发送认证请求消息。 作为响应，认证站发送认证数据以在第一级认证该站。
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公开(公告)号：US20130107443A1
公开(公告)日：2013-05-02
申请号：US13665181
申请日：2012-10-31
发明人： Jin-Ki KIM , DaeHee YI , HyoShin KIM
IPC分类号： G06F1/16
CPC分类号： G11C5/04 , G11C7/1003
摘要： A mass storage memory module system including a memory module having memory holding members which can be connected to each other, and removably connected to a memory controller. One or more modular memory holding members can be connected to each other to expand the overall storage capacity of the memory module. The presently described expandable memory module does not have a storage capacity limit. A memory holding member includes a plate, a plane, a board and another material having at least one memory device, or, on which at least one memory device is held or to which at least one memory device is mounted.
摘要翻译： 一种大容量存储器模块系统，包括具有能够彼此连接的存储器保持部件的存储器模块，并且可移除地连接到存储器控制器。 一个或多个模块化存储器保持构件可以彼此连接以扩展存储器模块的总体存储容量。 目前描述的可扩展存储器模块不具有存储容量限制。 存储器保持构件包括板，平面，板和具有至少一个存储器件的另一种材料，或者在其上保持至少一个存储器件或至少一个存储器件被安装在该存储器件上。
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公开(公告)号：US20130046921A1
公开(公告)日：2013-02-21
申请号：US13655582
申请日：2012-10-19
发明人： Hong Beom PYEON
IPC分类号： G06F12/00
CPC分类号： G06F3/0664 , G06F3/061 , G06F3/0625 , G06F3/068 , G06F9/4408 , G06F12/0868 , G06F2212/217 , Y02D10/13 , Y02D10/154
摘要： A system, method and machine-readable medium are provided to configure a non-volatile memory (NVM) including a plurality of NVM modules, in a system having a hard disk drive (HDD) and an operating system (O/S). In response to a user selection of a hybrid drive mode for the NVM, the plurality of NVM modules are ranked according to speed performance. Boot portions of the O/S are copied to a highly ranked NVM module, or a plurality of highly ranked NVM modules, and the HDD and the highly ranked NVM modules are assigned as a logical hybrid drive of the computer system. Ranking each of the plurality of NVM modules can include carrying out a speed performance test. This approach can provide hybrid disk performance using conventional hardware, or enhance performance of an existing hybrid drive, while taking into account relative performance of available NVM modules.
摘要翻译： 在具有硬盘驱动器（HDD）和操作系统（O / S）的系统中，提供了一种系统，方法和机器可读介质来配置包括多个NVM模块的非易失性存储器（NVM）。 响应于用户选择NVM的混合驱动模式，根据速度性能对多个NVM模块进行排序。 O / S的引导部分被复制到高排名的NVM模块或多个高排名的NVM模块，并且HDD和高排名的NVM模块被分配为计算机系统的逻辑混合驱动器。 对多个NVM模块中的每一个进行排序可以包括进行速度性能测试。 这种方法可以使用常规硬件提供混合磁盘性能，或提高现有混合驱动器的性能，同时考虑可用的NVM模块的相对性能。
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公开(公告)号：US11948629B2
公开(公告)日：2024-04-02
申请号：US18109390
申请日：2023-02-14
发明人： HakJune Oh , Hong Beom Pyeon , Jin-Ki Kim
CPC分类号： G11C11/5628 , G06F1/12 , G11C7/1021 , G11C7/1051 , G11C7/1078 , G11C11/5642 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3445 , G11C16/06 , G11C2207/107
摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.
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公开(公告)号：US11347396B2
公开(公告)日：2022-05-31
申请号：US16950204
申请日：2020-11-17
发明人： Peter B. Gillingham , Graham Allan
IPC分类号： G11C8/00 , G06F3/06 , G06F13/16 , G11C7/10 , G11C7/22 , G11C16/10 , G11C16/28 , G11C16/32 , G11C16/04 , G11C14/00 , H03K5/00
摘要： A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.
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公开(公告)号：USRE49018E1
公开(公告)日：2022-04-05
申请号：US16407380
申请日：2019-05-09
发明人： Dieter Haerle
摘要： A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.
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公开(公告)号：US20210408301A1
公开(公告)日：2021-12-30
申请号：US17369007
申请日：2021-07-07
发明人： Hyoung Seub Rhie
IPC分类号： H01L29/792 , H01L29/66 , G11C16/04 , H01L27/11573 , H01L27/11582 , G11C11/56
摘要： Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.
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公开(公告)号：US09117527B2
公开(公告)日：2015-08-25
申请号：US14158116
申请日：2014-01-17
发明人： Jin-Ki Kim
CPC分类号： G11C16/08 , G11C8/08 , G11C8/10 , G11C15/046 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/26
摘要： A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.
摘要翻译： 具有至少一个存储体的闪速存储器件，其中每个存储体具有可独立配置的页面大小。 每个存储体包括至少两个具有对应页面缓冲器的存储器平面，其中响应于配置数据和地址数据，同时选择性地访问存储器层的任何数量和组合。 在上电时，可以将组态数据加载到存储设备中，以进行存储体的静态页面配置，或者可以通过每个命令接收配置数据以允许存储体的动态页面配置。 通过选择性地调整存储体的页面大小，相应地调整块大小。
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